Kyle Rupnow - RankMe

49 papers A* 2A 13B 5Misc 5Journal 12Unranked 12

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems. MLSys Xiaofan Zhang, Haoming Lu, Cong Hao, Jiachen Li, Bowen Cheng, Yuhong Li, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-Mei Hwu, Deming Chen
2019	A*	`conf`	FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge. DAC Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, Kyle Rupnow, Wen-Mei Hwu, Deming Chen
2019	J	`jnl`	FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge. CoRR Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, Kyle Rupnow, Wen-Mei Hwu, Deming Chen
2019	J	`jnl`	Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Keith A. Campbell, David Lin, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Subhasish Mitra, Deming Chen
2019	J	`jnl`	SkyNet: A Champion Model for DAC-SDC on Low Power Object Detection. CoRR Xiaofan Zhang, Cong Hao, Haoming Lu, Jiachen Li, Yuhong Li, Yuchen Fan, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-Mei Hwu, Deming Chen
2019	J	`jnl`	SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems. CoRR Xiaofan Zhang, Haoming Lu, Cong Hao, Jiachen Li, Bowen Cheng, Yuhong Li, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-mei W. Hwu, Deming Chen
2017	A	`conf`	Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling. FPGA Sitao Huang, Gowthami Jayashri Manikandan, Anand Ramachandran, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen
2017	B	`conf`	High-performance video content recognition with long-term recurrent convolutional network for FPGA. FPL Xiaofan Zhang, Xinheng Liu, Anand Ramachandran, Chuanhao Zhuge, Shibin Tang, Peng Ouyang, Zuofu Cheng, Kyle Rupnow, Deming Chen
2017	A	`conf`	Machine learning on FPGAs to face the IoT revolution. ICCAD Xiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, Deming Chen
2017	A	`conf`	Machine learning on FPGAs to face the IoT revolution. ICCAD Xiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, Deming Chen
2016	Misc	`conf`	Acceleration of the Pair-HMM Algorithm for DNA Variant Calling. FCCM Gowthami Jayashri Manikandan, Sitao Huang, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen
2016	J	`jnl`	An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yun Liang, Muhammad Teguh Satria, Kyle Rupnow, Deming Chen
2016	Misc	`conf`	AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS. FCCM Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow
2016	A	`conf`	Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only). FPGA Liwei Yang, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow
2016	A*	`conf`	Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation. DAC Keith A. Campbell, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Deming Chen
2016	—	`conf`	Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis. ASP-DAC Zelei Sun, Keith A. Campbell, Wei Zuo, Kyle Rupnow, Swathi T. Gurumani, Frederic Doucet, Deming Chen
2016	J	`jnl`	FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Chen, Tan Nguyen, Yao Chen, Swathi T. Gurumani, Yun Liang, Kyle Rupnow, Jason Cong, Wen-mei W. Hwu, Deming Chen
2016	J	`jnl`	FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow. IEEE Trans. Very Large Scale Integr. Syst. Yao Chen, Swathi T. Gurumani, Yun Liang, Guofeng Li, Donghui Guo, Kyle Rupnow, Deming Chen
2016	A	`conf`	FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler. FPGA Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen
2016	A	`conf`	High Level Synthesis of Complex Applications: An H.264 Video Decoder. FPGA Xinheng Liu, Yao Chen, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen
2016	J	`jnl`	Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs. IET Cyper-Phys. Syst.: Theory & Appl. Deming Chen, Jason Cong, Swathi T. Gurumani, Wen-mei W. Hwu, Kyle Rupnow, Zhiru Zhang
2016	A	`conf`	Real-time system-level implementation of a telepresence robot using an embedded GPU platform. DATE Muhammad Teguh Satria, Swathi T. Gurumani, Wang Zheng, Keng Peng Tee, Augustine Koh, Pan Yu, Kyle Rupnow, Deming Chen
2016	—	`conf`	SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow. ISVLSI Tan Nguyen, Yao Chen, Kyle Rupnow, Swathi T. Gurumani, Deming Chen
2015	—	`conf`	Behavioral-level IP integration in high-level synthesis. FPT Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow
2015	J	`jnl`	Efficient GPU Spatial-Temporal Multitasking. IEEE Trans. Parallel Distributed Syst. Yun Liang, Huynh Phung Huynh, Kyle Rupnow, Rick Siow Mong Goh, Deming Chen
2015	—	`conf`	JIT trace-based verification for high-level synthesis. FPT Liwei Yang, Magzhan Ikram, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow
2015	—	`conf`	System-level design solutions: Enabling the IoT explosion. ASICON Liwei Yang, Yao Chen, Wei Zuo, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen
2014	A	`conf`	Fast and effective placement and routing directed high-level synthesis for FPGAs. FPGA Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen
2014	J	`jnl`	High-Level Synthesis With Behavioral-Level Multicycle Path Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow
2014	Misc	`conf`	Integrated CUDA-to-FPGA Synthesis with Network-on-Chip. FCCM Swathi T. Gurumani, Jacob Tolar, Yao Chen, Yun Liang, Kyle Rupnow, Deming Chen
2014	—	`conf`	New solutions for system-level and high-level synthesis (Invited paper). ISIC Wei Zuo, Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen
2013	—	`conf`	High-level synthesis of multiple dependent CUDA kernels on FPGA. ASP-DAC Swathi T. Gurumani, Hisham Cholakkal, Yun Liang, Kyle Rupnow, Deming Chen
2013	B	`conf`	High-level synthesis with behavioral level multi-cycle path analysis. FPL Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow
2013	A	`conf`	Improving high level synthesis optimization opportunity through polyhedral transformations. FPGA Wei Zuo, Yun Liang, Peng Li, Kyle Rupnow, Deming Chen, Jason Cong
2013	—	`conf`	Register and thread structure optimization for GPUs. ASP-DAC Yun Liang, Zheng Cui, Kyle Rupnow, Deming Chen
2012	A	`conf`	An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization. IPDPS Zheng Cui, Yun Liang, Kyle Rupnow, Deming Chen
2012	J	`jnl`	High-Level Synthesis: Productivity, Performance, and Software Constraints. J. Electr. Comput. Eng. Yun Liang, Kyle Rupnow, Yinan Li, Dongbo Min, Minh N. Do, Deming Chen
2012	A	`conf`	Real-time implementation and performance optimization of 3D sound localization on GPUs. DATE Yun Liang, Zheng Cui, Shengkui Zhao, Kyle Rupnow, Yihao Zhang, Douglas L. Jones, Deming Chen
2011	—	`conf`	A study of high-level synthesis: Promises and challenges. ASICON Kyle Rupnow, Yun Liang, Yinan Li, Deming Chen
2011	—	`conf`	High level synthesis of stereo matching: Productivity, performance, and software constraints. FPT Kyle Rupnow, Yun Liang, Yinan Li, Dongbo Min, Minh N. Do, Deming Chen
2011	J	`jnl`	Scientific Application Demands on a Reconfigurable Functional Unit Interface. ACM Trans. Reconfigurable Technol. Syst. Kyle Rupnow, Keith D. Underwood, Katherine Compton
2010	B	`conf`	A Reconfigurable Computing Scheduler Optimized for Multicore Systems. FPL Philip Garcia, Kyle Rupnow, Katherine Compton
2010	A	`conf`	Accurately evaluating application performance in simulated hybrid multi-tasking systems. FPGA Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton
2010	B	`conf`	Dynamic Binding and Scheduling of Firm-Deadline Tasks on Heterogeneous Compute Resources. RTCSA Hsiang-Kuo Tang, Kyle Rupnow, Parmesh Ramanathan, Katherine Compton
2009	Misc	`conf`	Block, Drop or Roll(back): Alternative Preemption Methods for RH Multi-Tasking. FCCM Kyle Rupnow, Wenyin Fu, Katherine Compton
2009	B	`conf`	Performance metrics for hybrid multi-tasking systems. FPL Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton
2007	—	`conf`	Reconfigurable Functional Units for Scientific Superscalar Processors. FPT Jonathan Evans, Kyle Rupnow, Katherine Compton
2007	Misc	`conf`	Scientific Application Acceleration with Reconfigurable Functional Units. FCCM Kyle Rupnow, Keith D. Underwood, Katherine Compton
2006	A	`conf`	Scientific applications vs. SPEC-FP: a comparison of program behavior. ICS Kyle Rupnow, Arun Rodrigues, Keith D. Underwood, Katherine Compton