Kyle Kuan

14 papers A 1C 1Journal 7Unranked 4

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. CoRR Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija
2022	—	`conf`	A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation. ISVLSI Kyle Kuan, Tosiron Adegbija
2021	—	`—`	Advancing STTRAM Caches for Runtime Adaptable Energy-Efficient Microarchitectures. Kyle Kuan
2020	C	`conf`	A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. ICCD Kyle Kuan, Tosiron Adegbija
2020	J	`jnl`	A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. CoRR Kyle Kuan, Tosiron Adegbija
2020	J	`jnl`	Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kyle Kuan, Tosiron Adegbija
2019	—	`conf`	Energy and Performance Analysis of STTRAM Caches for Mobile Applications. MCSoC Kyle Kuan, Tosiron Adegbija
2019	J	`jnl`	Energy and Performance Analysis of STTRAM Caches for Mobile Applications. CoRR Kyle Kuan, Tosiron Adegbija
2019	J	`jnl`	Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. CoRR Kyle Kuan, Tosiron Adegbija
2019	J	`jnl`	HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. CoRR Kyle Kuan, Tosiron Adegbija
2019	J	`jnl`	HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. IEEE Trans. Computers Kyle Kuan, Tosiron Adegbija
2019	—	`conf`	MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache. ACM Great Lakes Symposium on VLSI Kyle Kuan, Tosiron Adegbija
2019	—	`conf`	SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. IGSC Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija
2018	A	`conf`	LARS: Logically adaptable retention time STT-RAM cache for embedded systems. DATE Kyle Kuan, Tosiron Adegbija