Kyeongho Lee - RankMe

29 papers A* 3A 3B 3C 3Journal 15Unranked 2

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Design Framework of Heterogeneous Approximate DCIM-Based Accelerator for Energy-Efficient NN Processing. IEEE Trans. Circuits Syst. I Regul. Pap. Kyeongho Lee, Hyeyeong Lee, Jongsun Park
2024	J	`jnl`	A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations. IEEE J. Solid State Circuits Kyeongho Lee, Joonhyung Kim, Jongsun Park
2024	A	`conf`	TP-DCIM: Transposable Digital SRAM CIM Architecture for Energy-Efficient and High Throughput Transformer Acceleration. ICCAD Junwoo Park, Kyeongho Lee, Jongsun Park
2023	J	`jnl`	A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. Sungsoo Cheon, Kyeongho Lee, Jongsun Park
2023	J	`jnl`	Low Area and Low Power Threshold Implementation Design Technique for AES S-Box. IEEE Trans. Circuits Syst. II Express Briefs Junhyun Song, Kyeongho Lee, Jongsun Park
2022	—	`conf`	A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. AICAS Hyunchul Park, Kyeongho Lee, Jongsun Park
2022	A	`conf`	A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. ISLPED Joonhyung Kim, Kyeongho Lee, Jongsun Park
2022	J	`jnl`	A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. CoRR Joonhyung Kim, Kyeongho Lee, Jongsun Park
2022	A	`conf`	Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion. ICCAD Kyeongho Lee, Joonhyung Kim, Jongsun Park
2021	J	`jnl`	A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge. IEEE J. Solid State Circuits Kyeongho Lee, Woong Choi, Jongsun Park
2021	A*	`conf`	A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration. DAC Kyeongho Lee, Sungsoo Cheon, Joongho Jo, Woong Choi, Jongsun Park
2020	A*	`conf`	Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. DAC Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park
2020	J	`jnl`	Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. CoRR Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park
2019	C	`conf`	Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme. ISCAS Kyeongho Lee, Geon Ko, Jongsun Park
2018	A*	`conf`	Content addressable memory based binarized neural network accelerator using time-domain signal processing. DAC Woong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park
2018	C	`conf`	Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme. ISCAS Woong Choi, Kyeongho Lee, Jongsun Park
2015	B	`conf`	A Preliminary Study on Human Trust Measurements by EEG for Human-Machine Interactions. HAI Suh-Yeon Dong, Bo-Kyeong Kim, Kyeongho Lee, Soo-Young Lee
2015	B	`conf`	Implicit Shopping Intention Recognition with Eye Tracking Data and Response Time. HAI Dong-Gun Lee, Kyeongho Lee, Soo-Young Lee
2008	B	`conf`	Wire-speed application flow generation in hardware platform for multi-gigabit traffic monitoring. NOMS Taesang Choi, Sangsik Yoon, Dongwon Kang, Sangwan Kim, Joonkyung Lee, Kyeongho Lee
2006	C	`conf`	Novel Traffic Measurement Methodology for High Precision Applications Awareness in Multi-gigabit Networks. APNOMS Taesang Choi, Sangsik Yoon, Dongwon Kang, Sangwan Kim, Joonkyung Lee, Kyeongho Lee
2005	J	`jnl`	Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer. IEEE J. Solid State Circuits Hyungki Huh, Yido Koo, Kang-Yoon Lee, Yeonkyeong Ok, Sungho Lee, Daehyun Kwon, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim
2003	J	`jnl`	Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver. IEEE J. Solid State Circuits Kang-Yoon Lee, Seung-Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim
2002	J	`jnl`	A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems. IEEE J. Solid State Circuits Yido Koo, Hyungki Huh, Yongsik Cho, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim
2001	J	`jnl`	A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique. IEEE J. Solid State Circuits Kyeongho Lee, Joonbae Park, Jeong-Woo Lee, Seung-Wook Lee, Hyung Ki Huh, Deog-Kyoon Jeong, Wonchan Kim
2000	J	`jnl`	An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. IEEE J. Solid State Circuits Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim
1999	—	`conf`	A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. CICC Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim
1998	J	`jnl`	1.04 GBd low EMI digital video interface system using small swing serial link technique. IEEE J. Solid State Circuits Kyeongho Lee, Yeshik Shin, Sungjoon Kim, Deog-Kyoon Jeong, Gyudong Kim, Bruce Kim, Victor Da Costa
1997	J	`jnl`	A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL. IEEE J. Solid State Circuits Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim
1995	J	`jnl`	A CMOS serial link for fully duplexed data communication. IEEE J. Solid State Circuits Kyeongho Lee, Sungjoon Kim, Gijung Ahn, Deog-Kyoon Jeong