Kwen-Siong Chong

84 papers A 1C 31Journal 25Unranked 27
YearRankTypeTitle / Venue / Authors
2025 C conf
An Adaptive AI-based Approach to Detect and Protect COTS Systems against Micro-Single-Event-Latchups (μ-SELs) and SELs.
ISCAS
Junkai Zhao, Yin Sun, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang
2025 — conf
An Improved AI-Based Micro-Single-Event-Latchup (Micro-SEL) and SEL Detection in a COTS System Against R/C/L-Induced (Power Management) Distortions.
ICECS
Junkai Zhao, Caoyang Yu, Jiwei Wang, Yin Sun, Tony Zhang, Tong Ge, Kwen-Siong Chong, Wei Shu, Joseph S. Chang
2025 C conf
Live Demonstration: AI-based System Latchup Detection and Protection for COTS Systems.
ISCAS
Yin Sun, Junkai Zhao, Rouli Fang, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang
2025 C conf
N-MUX: Neighborhood-Based Logic Locking Against Machine Learning Attacks.
ISCAS
Han Zhang, Xuenong Hong, Shirui Sheng, Juncheng Chen, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
2024 — conf
A Novel Multi-Error-Lock-Trace (MELT) Test Structure for SET/SEU Characterization of Radiation-Hardened-By-Design Cells.
MWSCAS
Rouli Fang, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Wei Shu, Sun-Yang Tay, Joseph Sylvester Chang
2024 C conf
A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix.
ISCAS
Juncheng Chen, Han Zhang, Zishuo Yang, Yicheng Xu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
2024 — conf
An Energy-Efficient and High-Accuracy Spiking Neural Network Utilizing Asynchronous CORDIC for On-FPGA STDP Learning.
APCCAS
Shirui Sheng, Kwen-Siong Chong, Jun-Sheng Ng, Zhiping Lin, Joseph S. Chang, Bah-Hwee Gwee
2024 J jnl
Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine.
IEEE Trans. Very Large Scale Integr. Syst.
Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Kwen-Siong Chong, Bah-Hwee Gwee
2023 C conf
Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs.
ISCAS
Jun-Sheng Ng, Juncheng Chen, Si Wu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
2022 J jnl
A High-Accuracy and Energy-Efficient CORDIC Based Izhikevich Neuron With Error Suppression and Compensation.
IEEE Trans. Biomed. Circuits Syst.
Jipeng Wang, Zixuan Peng, Yi Zhan, Yujie Li, Guoyi Yu, Kwen-Siong Chong, Chao Wang
2022 J jnl
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks.
IEEE Trans. Very Large Scale Integr. Syst.
Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2022 C conf
An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations.
ISCAS
Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2022 J jnl
Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices.
Sensors
Xvpeng Zhang, Bingqiang Liu, Yaqi Zhao, Xiaoyu Hu, Zixuan Shen, Zhaoxia Zheng, Zhenglin Liu, Kwen-Siong Chong, Guoyi Yu, Chao Wang, Xuecheng Zou
2022 — conf
Incremental Linear Regression Attack.
AsianHOST
Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Zhili Zou, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
2022 C conf
Non-profiling based Correlation Optimization Deep Learning Analysis.
ISCAS
Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee
2021 — conf
A High-Accuracy and Energy-Efficient CORDIC based Izhikevich Neuron.
NEWCAS
Zixuan Peng, Jipeng Wang, Yi Zhan, Run Min, Guoyi Yu, Jianwen Luo, Kwen-Siong Chong, Chao Wang
2021 J jnl
A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures.
IEEE Trans. Inf. Forensics Secur.
Juncheng Chen, Jun-Sheng Ng, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee
2021 J jnl
A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection.
IEEE Trans. Circuits Syst. II Express Briefs
Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2021 J jnl
An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Jiajun Wu, Xuan Huang, Le Yang, Jipeng Wang, Bingqiang Liu, Ziyuan Wen, Juhui Li, Guoyi Yu, Kwen-Siong Chong, Chao Wang
2021 J jnl
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Kwen-Siong Chong, Jun-Sheng Ng, Juncheng Chen, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Joseph Sylvester Chang, Bah-Hwee Gwee
2021 C conf
Normalized Differential Power Analysis - for Ghost Peaks Mitigation.
ISCAS
Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee
2020 C conf
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.
ISCAS
Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2020 C conf
A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES).
ISCAS
Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
2020 C conf
A Secure Data-Toggling SRAM for Confidential Data Protection.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2020 — conf
An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity.
A-SSCC
Jiajun Wu, Xuan Huang, Le Yang, Liang Wang, Jipeng Wang, Zuozhu Liu, Kwen-Siong Chong, Shaowei Lin, Chao Wang
2020 — conf
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC.
APCCAS
Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
2020 — conf
High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications.
ISOCC
Weng-Geng Ho, Ali Akbar Pammu, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
2020 C conf
Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller.
ISCAS
Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Wei Shu, Joseph S. Chang
2019 J jnl
A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor.
IEEE Trans. Inf. Forensics Secur.
Ali Akbar Pammu, Weng-Geng Ho, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
2019 J jnl
A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning on Physical Leakage Information.
IEEE Trans. Dependable Secur. Comput.
Ali Akbar Pammu, Kwen-Siong Chong, Yi Wang, Bah-Hwee Gwee
2019 J jnl
A Secure Data-Toggling SRAM for Confidential Data Protection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2019 C conf
Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design.
ISCAS
Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, Wei Shu, Joseph S. Chang, Bah-Hwee Gwee
2019 — conf
Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications.
SoCC
Weng-Geng Ho, Ali Akbar Pammu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee
2019 — conf
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.
AsianHOST
Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang
2018 — conf
A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation.
DSP
Weng-Geng Ho, Zixian Zheng, Kwen-Siong Chong, Bah-Hwee Gwee
2018 J jnl
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design.
IEEE Trans. Very Large Scale Integr. Syst.
Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang
2018 — conf
Radiation Hardening By Design Integrated Circuits Enabling Low-Cost Satellites for Internet-of-Things.
DSP
Wei Shu, Jize Jiang, Kwen-Siong Chong, Joseph Sylvester Chang
2018 — conf
Single-Event-Transient Resilient Memory for DSP in Space Applications.
DSP
Ne Kyaw Zwa Lwin, H. Sivaramakrishnan, Kwen-Siong Chong, Tong Lin, Wei Shu, Joseph S. Chang
2017 C conf
DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer.
ISCAS
James Lim, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
2017 C conf
Highly secured state-shift local clock circuit to countermeasure against side channel attack.
ISCAS
Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee
2017 J jnl
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template.
IEEE Trans. Very Large Scale Integr. Syst.
Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2016 C conf
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM.
ISCAS
Weng-Geng Ho, Kyaw Zwa Lwin Ne, N. Prashanth Srinivas, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2016 C conf
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process.
ISCAS
Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang
2016 C conf
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits.
ISCAS
Weng-Geng Ho, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2016 — conf
Highly secured arithmetic hiding based S-Box on AES-128 implementation.
ISIC
Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee
2016 — conf
Interceptive side channel attack on AES-128 wireless communications for IoT applications.
APCCAS
Ali Akbar Pammu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee
2016 A conf
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications.
DATE
Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee, Joseph Sylvester Chang
2016 — conf
Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture.
NAS
Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee
2016 — conf
Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack.
ISIC
Weng-Geng Ho, Ali Akbar Pammu, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee
2016 — conf
Success rate model for fully AES-128 in correlation power analysis.
APCCAS
Ali Akbar Pammu, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Nan Liu, Bah-Hwee Gwee
2016 C conf
Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process.
ISCAS
Jize Jiang, Wei Shu, Kwen-Siong Chong, Tong Lin, Ne Kyaw Zwa Lwin, Joseph Sylvester Chang, Jingyuan Liu
2015 C conf
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline.
ISCAS
Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2015 C conf
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC).
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang
2015 J jnl
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer.
IET Circuits Devices Syst.
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2014 J jnl
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2014 — conf
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation.
ISIC
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Ne Kyaw Zwa Lwin
2014 — conf
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips.
APCCAS
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2014 — conf
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process.
MWSCAS
Joseph S. Chang, Kwen-Siong Chong, Wei Shu, Tong Lin, Jize Jiang, Ne Kyaw Zwa Lwin, Yang Kang
2014 C conf
Synthesis of asynchronous QDI circuits using synchronous coding specifications.
ISCAS
Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho
2014 J jnl
Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing.
Circuits Syst. Signal Process.
Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee
2013 — conf
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS.
ACM Great Lakes Symposium on VLSI
Jaeyoung Kim, Kwen-Siong Chong, Joseph Sylvester Chang, Pinaki Mazumder
2013 C conf
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic.
ISCAS
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2013 J jnl
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive V
IEEE J. Solid State Circuits
Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2013 C conf
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2013 J jnl
Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Kok-Leong Chang, Joseph S. Chang, Bah-Hwee Gwee, Kwen-Siong Chong
2012 C conf
A comparative study on asynchronous Quasi-Delay-Insensitive templates.
ISCAS
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2012 C conf
An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability.
ISCAS
Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2012 — conf
Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques.
ISED
Kwen-Siong Chong, Joseph S. Chang, Idongesit E. Ebong, Yalcin Yilmaz, Pinaki Mazumder
2012 C conf
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2012 J jnl
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors.
IEEE J. Solid State Circuits
Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang
2011 C conf
A low-power dual-rail inputs write method for bit-interleaved memory cells.
ISCAS
Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2011 C conf
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, Yin Sun, Kok-Leong Chang
2009 J jnl
A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bah-Hwee Gwee, Joseph S. Chang, Yiqiong Shi, Chien-Chung Chua, Kwen-Siong Chong
2009 C conf
Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic.
ISCAS
Tong Lin, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2007 C conf
A Low Energy FFT/IFFT Processor for Hearing Aids.
ISCAS
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2007 J jnl
Design of several asynchronous-logic macrocells for a low-voltage micropower cell library.
IET Circuits Devices Syst.
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2007 J jnl
Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors.
IEEE J. Solid State Circuits
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2007 J jnl
Low energy 16-bit Booth leapfrog array multiplier using dynamic adders.
IET Circuits Devices Syst.
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2006 J jnl
A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids.
IEEE Trans. Circuits Syst. II Express Briefs
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2005 J jnl
A micropower low-voltage multiplier with reduced spurious switching.
IEEE Trans. Very Large Scale Integr. Syst.
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2005 — conf
Low-voltage micropower multipliers with reduced spurious switching.
ISCAS (4)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2004 — conf
A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders.
ISCAS (2)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2002 — conf
Low-voltage asynchronous adders for low power and high speed applications.
ISCAS (1)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2002 — conf
Low-voltage micropower asynchronous multiplier for hearing instruments.
ISCAS (1)
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang