Kwanyeob Chae - RankMe

19 papers A 1C 1Journal 4Unranked 13

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	37.3 A 2nm All-Digital 14.4Gb/s/pin LPDDR6 PHY with Quarter-Rate Clocking Architecture and Multi-Level FIFO-Based Speculative DFE. ISSCC Yoonjae Choi, Daero Kim, Myunggon Kim, Sangmin Lee, Hansol Kang, Gwangwon Lee, Yoonhyung Kim, Sungsik Kang, Hyun Cho, Boyoung Kang, Kyoungwon Lee, Jaegeun Song, Jinho Choi, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Hyo-Gyuem Rhew
2024	J	`jnl`	A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. IEEE J. Solid State Circuits Kwanyeob Chae, Jaegeun Song, Yoonjae Choi, Jiyeon Park, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Kyeongkeun Kang, Eunsu Kim, Juyoung Kim, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo Gyuem Rhew, Jongshin Shin
2024	—	`conf`	A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM. A-SSCC Yoonjae Choi, Jaegeun Song, Daero Kim, Myunggon Kim, Jiyeon Park, Jinho Choi, Changki Kwon, Minho Seo, Jihun Oh, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Jongshin Shin
2023	—	`conf`	A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. ISSCC Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyogyuem Rhew, Jongshin Shin
2020	—	`conf`	22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique. ISSCC Soo-Min Lee, Kihwan Seong, Joohee Shin, Hyoungjoong Kim, Jaehyun Jeong, Shinyoung Yi, Juyoung Kim, Eunsu Kim, Sukhyun Jung, Sangyun Hwang, Jihun Oh, Kwanyeob Chae, Kyounghoi Koo, Sanghune Park, Jongshin Shin, Jaehong Park
2019	—	`conf`	An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. VLSI Circuits Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko
2018	—	`conf`	Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface. ISOCC Kwanyeob Chae, Billy Koo, Jihun Oh, Sanghune Park, Jongshin Shin, Jaehong Park
2017	—	`conf`	23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller. ISSCC Soo-Min Lee, Jihun Oh, Jinho Choi, Seokkyun Ko, Daero Kim, Kyounghoi Koo, JongRyun Choi, Yoonjee Nam, Sangsoo Park, Hyungkweon Lee, Eunsu Kim, Sukhyun Jung, Kwanyeob Chae, Suho Kim, Sanghune Park, Sanghyun Lee, Sungho Park
2016	—	`conf`	A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology. ESSCIRC Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyunhyuck Kim, Hyungkwon Yi, Yoonjee Nam, Jinho Choi, Sanghune Park, Sanghyun Lee
2014	J	`jnl`	A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching. IEEE Trans. Circuits Syst. I Regul. Pap. Kwanyeob Chae, Saibal Mukhopadhyay
2014	J	`jnl`	Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating. IEEE Trans. Circuits Syst. II Express Briefs Kwanyeob Chae, Saibal Mukhopadhyay
2013	C	`conf`	Error resilient logic circuits under dynamic variations. IOLTS Kwanyeob Chae, Saibal Mukhopadhyay
2013	—	`conf`	On the impact of 3D integration on high-throughput sensor information processing: A case study with image sensing. NANOARCH Denny Lie, Kwanyeob Chae, Saibal Mukhopadhyay
2012	J	`jnl`	All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in a Low-Voltage Operation. IEEE Trans. Circuits Syst. II Express Briefs Kwanyeob Chae, Saibal Mukhopadhyay
2012	—	`conf`	Characterization of Inverse Temperature Dependence in logic circuits. CICC Minki Cho, Muhammad M. Khellah, Kwanyeob Chae, Khondker Zakir Ahmed, James W. Tschanz, Saibal Mukhopadhyay
2012	—	`conf`	Low-power design under variation using error prevention and error tolerance (invited paper). LATW Kwanyeob Chae, Minki Cho, Saibal Mukhopadhyay
2012	—	`conf`	Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs. ASP-DAC Kwanyeob Chae, Saibal Mukhopadhyay
2010	—	`conf`	A dynamic timing control technique utilizing time borrowing and clock stretching. CICC Kwanyeob Chae, Saibal Mukhopadhyay, Chang-Ho Lee, Joy Laskar
2004	A	`conf`	High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study. DATE Hye-On Jang, Minsoo Kang, Myeong-jin Lee, Kwanyeob Chae, Kookpyo Lee, Kyuhyun Shim