Kwanseo Park - RankMe

51 papers C 3Journal 35Unranked 13

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	37.9 A 14Gb/s/pin 0.163pJ/b DQ Receiver for HBM with Baud-Rate Phase Tracking Loop Supporting Background Offset Calibration. ISSCC Jeonghyeon Lee, Ho-Joon Shin, Han-Gon Ko, Kwanseo Park
2026	J	`jnl`	A 1.19-pJ/b 32-Gb/s Baud-Rate Receiver Employing 2UI Integrated Pattern-Based CDR and DFE Adaptation Without Data-Level Reference. IEEE J. Solid State Circuits Suil Kang, Sinho Lee, Young-Wook Kim, Junhak Kim, Ho-Joon Shin, Haram Ju, Kwangho Lee, Kwanseo Park
2026	J	`jnl`	A Pattern-Dependent Pulse Filtering Technique for Low-Jitter Injection-Locked CDR in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Junhak Kim, Young-Wook Kim, Sinho Lee, Yoojin Jung, Min-Seong Choo, Kwanseo Park
2025	J	`jnl`	A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces. IEEE Trans. Very Large Scale Integr. Syst. Jonghyun Oh, Kwanseo Park, Young-Ha Hwang
2025	J	`jnl`	A 14-to-32-Gb/s Deadzone-Free Referenceless CDR With Autocovariance-Based Seamless Frequency Detector in 40-nm CMOS Technology. IEEE J. Solid State Circuits Hong-Seok Choi, Jae-Geon Lee, Seung-Hwan Gong, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyungrok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Kwanseo Park, Min-Seong Choo
2025	J	`jnl`	A 16-to-30-Gb/s 1.03-pJ/b Baud-Rate Receiver With Referenceless CDR Employing Integrated Pattern Decoding Technique in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Yoojin Jung, Young-Wook Kim, Sinho Lee, Suil Kang, Kwanseo Park
2025	J	`jnl`	A Compact Power-on-Reset Circuit With Configurable Brown-Out Detection. IEEE Trans. Very Large Scale Integr. Syst. Yoochang Kim, Jun-Eun Park, Kwanseo Park, Young-Ha Hwang
2025	J	`jnl`	A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver. IEEE Trans. Circuits Syst. I Regul. Pap. Sinho Lee, Daeun Yun, Junhak Kim, Suil Kang, Young-Wook Kim, Kwangho Lee, Haram Ju, Sanghee Lee, Kwanseo Park
2025	J	`jnl`	An 18-Tb/s/mm PAM-3 On-Chip Link With Jitter-Suppressing 3T4T Coding and FFE-Based Crosstalk Cancellation for Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. Dongwoo Kang, Jun-Soo Park, Young-Wook Kim, Sinho Lee, Kyugun Kim, Han-Gon Ko, Kwanseo Park
2024	J	`jnl`	A 0.09-pJ/b/dB 28-Gb/s Digital CDR With ISI-Resistant Phase Detector. IEEE Trans. Circuits Syst. II Express Briefs Suil Kang, Dongwoo Kang, Sinho Lee, Minkyo Shim, Seungha Roh, Sunjin Choi, Kwanseo Park
2024	—	`conf`	A 16-30Gb/s 1.03pJ/b Referenceless Baud-Rate CDR with Integrated Pattern Decoding Technique for Fast Frequency Acquisition. A-SSCC Yoojin Jung, Young-Wook Kim, Sinho Lee, Suil Kang, Kwanseo Park
2024	C	`conf`	A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. ISCAS Zhongkai Wang, Minsoo Choi, Paul Kwon, Zhaokai Liu, Bozhi Yin, Kyoungtae Lee, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon
2024	J	`jnl`	A 3×12 -Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Dongwoo Kang, Han-Gon Ko, Kwanseo Park
2024	J	`jnl`	A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Minkyo Shim, Seungha Roh, Yunhee Lee, Jung-Woo Sull, Deog-Kyoon Jeong, Kwanseo Park
2024	J	`jnl`	A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR. IEEE Trans. Circuits Syst. I Regul. Pap. Seungha Roh, Minkyo Shim, Yoojin Jung, Deog-Kyoon Jeong, Kwanseo Park
2024	J	`jnl`	Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery. IEEE Trans. Circuits Syst. II Express Briefs Young-Ha Hwang, Kwanseo Park
2023	J	`jnl`	A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation. IEEE Trans. Circuits Syst. II Express Briefs Minkyo Shim, Kwang-Hoon Lee, Seungha Roh, Kwanseo Park, Deog-Kyoon Jeong
2023	J	`jnl`	A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link. IEEE Access Minkyo Shim, Woonghee Lee, Yunhee Lee, Kwanseo Park, Deog-Kyoon Jeong
2023	J	`jnl`	A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS. IEEE J. Solid State Circuits Woosong Jung, Kwangho Lee, Kwanseo Park, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
2022	—	`conf`	A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. VLSI Technology and Circuits Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon
2022	J	`jnl`	An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS. IEEE J. Solid State Circuits Zhongkai Wang, Minsoo Choi, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon
2022	J	`jnl`	Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector. IEEE J. Solid State Circuits Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong
2022	J	`jnl`	Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector. IEEE J. Solid State Circuits Kwanseo Park, Minkyo Shim, Han-Gon Ko, Borivoje Nikolic, Deog-Kyoon Jeong
2021	—	`conf`	8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS. ISSCC Minsoo Choi, Zhongkai Wang, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Elad Alon
2021	J	`jnl`	A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. IEEE Access Byungjun Kang, Gyu-Seob Jeong, Jeongho Hwang, Kwanseo Park, Hyungrok Do, Hyojun Kim, Han-Gon Ko, Moon-Chul Choi, Deog-Kyoon Jeong
2021	J	`jnl`	A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. IEEE J. Solid State Circuits Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
2021	J	`jnl`	A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong
2021	J	`jnl`	An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Kwangho Lee, Hyojun Kim, Woosong Jung, Jinhyung Lee, Haram Ju, Kwanseo Park, Ook Kim, Deog-Kyoon Jeong
2020	—	`conf`	6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS. ISSCC Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong
2020	—	`conf`	6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. ISSCC Han-Gon Ko, Soyeong Shin, Jonghyun Oh, Kwanseo Park, Deog-Kyoon Jeong
2020	J	`jnl`	A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference. IEEE J. Solid State Circuits Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong
2019	—	`conf`	A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level. VLSI Circuits Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong
2019	J	`jnl`	A 10-Gb/s, 0.03-mm IEEE J. Solid State Circuits Min-Seong Choo, Kwanseo Park, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2019	J	`jnl`	A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs Min-Seong Choo, Yeonggeun Song, Sung-Yong Cho, Han-Gon Ko, Kwanseo Park, Deog-Kyoon Jeong
2019	J	`jnl`	A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. IEEE Trans. Circuits Syst. II Express Briefs Moon-Chul Choi, Deog-Kyoon Jeong, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim
2019	—	`conf`	A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. VLSI Circuits Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
2019	—	`conf`	A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. VLSI Circuits Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog-Kyoon Jeong
2019	J	`jnl`	A Modulo-FIR Equalizer for Wireline Communications. IEEE Trans. Circuits Syst. I Regul. Pap. Gyu-Seob Jeong, Byungjun Kang, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong
2018	J	`jnl`	25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs Gyu-Seob Jeong, Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han-Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2018	J	`jnl`	A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE. IEEE Trans. Circuits Syst. II Express Briefs Jinhyung Lee, Kwanseo Park, Kwangho Lee, Deog-Kyoon Jeong
2018	J	`jnl`	A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS. IEEE J. Solid State Circuits Kwanseo Park, Woo-Rham Bae, Jinhyung Lee, Jeongho Hwang, Deog-Kyoon Jeong
2018	J	`jnl`	A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. IEEE Trans. Ind. Electron. Woo-Rham Bae, Haram Ju, Kwanseo Park, Jaeduk Han, Deog-Kyoon Jeong
2017	—	`conf`	A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. CICC Kwanseo Park, Woo-Rham Bae, Deog-Kyoon Jeong
2017	J	`jnl`	A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. IEEE Trans. Circuits Syst. II Express Briefs Kwanseo Park, Jinhyung Lee, Kwangho Lee, Min-Seong Choo, Sungchun Jang, Sang-Hyeok Chu, Sungwoo Kim, Deog-Kyoon Jeong
2016	J	`jnl`	A 0.36 pJ/bit, 0.025 mm IEEE Trans. Circuits Syst. I Regul. Pap. Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong
2016	—	`conf`	A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS. A-SSCC Woo-Rham Bae, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong
2016	J	`jnl`	A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS. IEEE J. Solid State Circuits Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong
2015	C	`conf`	A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. ISCAS Kwanseo Park, Woo-Rham Bae, Haram Ju, Jinhyung Lee, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2015	—	`conf`	A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. A-SSCC Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong
2014	—	`conf`	A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. ESSCIRC Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong
2000	C	`conf`	Stabilization of linear systems via low-order dynamic output feedback: a passification approach. ACC Young Ik Son, Hyungbo Shim, Kwanseo Park, Jin Heon Seo