Kwang Sub Yoon

14 papers C 1Unranked 13
YearRankTypeTitle / Venue / Authors
2017 — conf
A CMOS third order ΔΣ modulator with inverter-based integrators.
SoCC
Jeong H. Choi, Kwang Sub Yoon
2016 — conf
A CMOS 10-bit SAR ADC with threshold configuring comparator for 5 MSBs.
ISOCC
Sang Heon Lee, Seong Jae Hyeon, Kim Jong Gu, Kwang Sub Yoon
2016 — conf
A CMOS buck converter with PFM / hysteretic mode.
ISOCC
Tae-Heon Lee, Jong-Gu Kim, Kwang Sub Yoon
2016 — conf
A low power fourth order ΣΔ CMOS modulator with subthreshold amplifier.
SoCC
Seong Jae Hyeon, Kwang Sub Yoon, Soo Hun Yang
2015 — conf
A CMOS hysteretic DC-DC buck converter with a low output ripple voltage.
ISQED
Tae-Jin Chung, Kwang Sub Yoon
2014 — conf
Design of a low power CMOS 10bit flash-SAR ADC.
SoCC
Gi-Yoon Lee, Kwang Sub Yoon
2013 — conf
A CMOS high dimming ratio power-LED driver with a preloading inductor current method.
ISQED
Kwang Sub Yoon, Keon Lee
2012 — conf
Design of high dimming ratio power-LED driver with preloading inductor current methodology.
ISOCC
Keon Lee, Dong-Hun Lee, Su-hun Yang, Ji-Hyun Park, Kwang Sub Yoon
2011 — conf
Design of a 12-b asynchronous SAR CMOS ADC.
ISOCC
Jinwoo Kim, Shin-Il Lim, Kwang Sub Yoon, Sangmin Lee
2004 — conf
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit.
ISMVL
Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim
2003 — conf
A dual band CMOS VCO with a balanced duty cycle buffer.
ACM Great Lakes Symposium on VLSI
Yun Cheol Han, Kwang Il Kim, Jun Kim, Kwang Sub Yoon
1999 — conf
A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range.
ISCAS (2)
Hyuk-Jun Sung, Kwang Sub Yoon
1996 — conf
A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load.
Great Lakes Symposium on VLSI
Jai-Sop Hyun, Kwang Sub Yoon
1995 C conf
A Precision Output Conductance Model for Analog CMOS Circuit Simulations.
ISCAS
Jong Kug Seon, Kwang Sub Yoon