Kwang-Jow Gan

14 papers B 1Journal 6Unranked 7
YearRankTypeTitle / Venue / Authors
2026 J jnl
Design and implementation of full adder using negative differential resistance circuits based on CMOS process.
Microelectron. J.
Kwang-Jow Gan, Li-Cheng Zhang
2013 J jnl
The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET.
Microelectron. Reliab.
Wen-Kuan Yeh, Po-Ying Chen, Kwang-Jow Gan, Jer-Chyi Wang, Chao-Sung Lai
2011 J jnl
Logic circuit design using monostable-bistable transition logic element based on standard BiCMOS process.
Microelectron. J.
Kwang-Jow Gan, Cher-Shiung Tsai, Yu-Kuang Li, Jenq-Jong Lu
2010 J jnl
Investigation of Adjustable Current-Voltage Characteristics and Hysteresis Phenomena for Multiple-Peak Negative Differential Resistance Circuit.
IEICE Trans. Electron.
Kwang-Jow Gan, Dong-Shong Liang
2010 J jnl
Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources.
IEICE Trans. Inf. Syst.
Kwang-Jow Gan, Dong-Shong Liang, Yan-Wun Chen
2009 — conf
Multiple-Valued Memory Design by Standard BiCMOS Technique.
CSIE (3)
Dong-Shong Liang, Kwang-Jow Gan, Jenq-Jong Lu, Cheng-Chi Tai, Cher-Shiung Tsai, Geng-Huang Lan, Yaw-Hwang Chen
2009 J jnl
Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio.
IEICE Trans. Electron.
Dong-Shong Liang, Kwang-Jow Gan, Cheng-Chi Tai, Cher-Shiung Tsai
2008 — conf
New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits.
DELTA
Dong-Shong Liang, Kwang-Jow Gan
2006 — conf
Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process.
APCCAS
Dong-Shong Liang, Cheng-Chi Tai, Kwang-Jow Gan, Cher-Shiung Tsai, Yaw-Hwang Chen
2006 — conf
Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process.
APCCAS
Kwang-Jow Gan, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen, Chun-Ming Wen
2006 B conf
The Design of MOS-NDR-Based Cellular Neural Network.
IJCNN
Dong-Shong Liang, Yaw-Hwang Chen, Chun-Min Wen, Chun-Da Tu, Kwang-Jow Gan, Cher-Shiung Tsai
2005 — conf
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits.
IWSOC
Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang
2005 — conf
Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process.
IWSOC
Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen
2005 — conf
Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits.
IWSOC
Dong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su