Kuruvilla Varghese

26 papers C 5Misc 7Journal 2Unranked 12

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	An FPGA Based Accelerator of the Bi-Directional Wavefront Algorithm for Pairwise Sequence Alignment. APCCAS Ajay S, Praveen V. S, Kuruvilla Varghese
2023	—	`conf`	Deep-Feature-Based Visual Odometry for Autonomous Emergency Parking. AIR Shrutheesh Raman Iyer, Kuruvilla Varghese, Raghu Krishnapuram, Panini Bhamidipati
2023	Misc	`conf`	Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core. VLSID Sajin S, Shubham Sunil Garag, Anuj Phegade, Deepshikha Gusain, Kuruvilla Varghese
2023	—	`conf`	Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder. APCCAS Sadhu Sai Ram, Kuruvilla Varghese
2023	—	`conf`	High Throughput Hardware Acceleration for Image Generation using HLS. APCCAS A. BhanuPrasad, Kuruvilla Varghese
2022	Misc	`conf`	A Soft RISC-V Vector Processor for Edge-AI. VLSID V. Naveen Chander, Kuruvilla Varghese
2022	Misc	`conf`	Hardware Accelerator for Capsule Network based Reinforcement Learning. VLSID Dola Ram, Suraj Panwar, Kuruvilla Varghese
2022	C	`conf`	High-Level Synthesis of Geant4 Particle Transport Application for FPGA. DSD Ramakant Joshi, Kuruvilla Varghese
2021	Misc	`conf`	Network Emulation For Tele-driving Application Development. COMSNETS Srikrishna Acharya, S. Sadgun S. Devanahalli, Alok Rawat, Kuruvilla Varghese, Pratik Sharma, Bharadwaj Amrutur, Ashish Joglekar, Raghu Krishnapuram, Yogesh Simmhan, Himanshu Tyagi
2020	—	`conf`	A RISC-V ISA Compatible Processor IP. VDAT Akshay Birari, Piyush Birla, Kuruvilla Varghese, Bharadwaj S. Amrutur
2020	C	`conf`	Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA. DSD T. Gokulan, Akshay Muraleedharan, Kuruvilla Varghese
2018	C	`conf`	FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training. DSD Sajna Remi Clere, Sachin Sethumadhavan, Kuruvilla Varghese
2018	J	`jnl`	Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network. IEEE Trans. Neural Networks Learn. Syst. Nimish Shah, Paragkumar Chaudhari, Kuruvilla Varghese
2017	—	`conf`	A Custom Designed RISC-V ISA Compatible Processor for SoC. VDAT Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Bharadwaj S. Amrutur
2017	—	`conf`	A high-throughput clock-less architecture for soft-output Viterbi detection. MWSCAS Arnab Dey, Sebin Jose, Kuruvilla Varghese, Shayan Garani Srinivasa
2016	Misc	`conf`	A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. VLSID Saugata Datta, Kuruvilla Varghese, Shayan Garani Srinivasa
2015	J	`jnl`	Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA. IEEE Trans. Very Large Scale Integr. Syst. Sriram Venkateshan, Alap Patel, Kuruvilla Varghese
2013	—	`conf`	Transparent FPGA based device for SQL DDoS mitigation. FPT Karthikeyan Pandiyarajan, Srijith Haridas, Kuruvilla Varghese
2012	Misc	`conf`	HD Resolution Intra Prediction Architecture for H.264 Decoder. VLSI Design Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese
2011	—	`conf`	A scalable network port scan detection system on FPGA. FPT Tejasvi Anand, Yagnesh Waghela, Kuruvilla Varghese
2010	—	`conf`	Area optimized H.264 Intra prediction architecture for 1080p HD resolution. ASAP Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese
2010	C	`conf`	In-channel Flow Control Scheme for Network-on-Chip. DSD Vrishali Vijay Nimbalkar, Kuruvilla Varghese
2010	C	`conf`	Space Efficient Diagonal Linear Space Sequence Alignment. BIBE Gandhi Arpit, Raghavendra Adiga, Kuruvilla Varghese
2009	—	`conf`	Power optimal Network-on-Chip interconnect design. SoCC G. Vikas, Joy Kuri, Kuruvilla Varghese
2008	Misc	`conf`	A Scalable High Throughput Firewall in FPGA. FCCM Gajanan S. Jedhe, Arun Ramamoorthy, Kuruvilla Varghese
2008	—	`conf`	Dynamically reconfigurable regular expression matching architecture. ASAP J. Divyasree, H. Rajashekar, Kuruvilla Varghese