Kurt Antreich

36 papers A* 7A 9C 1Journal 11Unranked 8
YearRankTypeTitle / Venue / Authors
2007 J jnl
Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guido Stehr, Helmut E. Graeb, Kurt Antreich
2004 A conf
Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing.
ICCAD
Guido Stehr, Helmut E. Graeb, Kurt Antreich
2003 A conf
Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification.
ICCAD
Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich
2003 A* conf
Performance trade-off analysis of analog circuits by normal-boundary intersection.
DAC
Guido Stehr, Helmut E. Graeb, Kurt Antreich
2002 A conf
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits.
DATE
Michael Pronath, Helmut E. Graeb, Kurt Antreich
2002 A* conf
Handling special constructs in symbolic simulation.
DAC
Alfred Kölbl, James H. Kukula, Kurt Antreich, Robert F. Damiano
2001 — conf
A fast method for identifying matching-relevant transistor pairs.
CICC
Frank Schenkel, Michael Pronath, Helmut Graeb, Kurt Antreich
2001 A* conf
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search.
DAC
Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich
2001 A conf
The Sizing Rules Method for Analog Integrated Circuit Design.
ICCAD
Helmut E. Graeb, Stephan Zizala, Josef Eckmüller, Kurt Antreich
2000 J jnl
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Paul Tafertshofer, Andreas Ganz, Kurt Antreich
2000 A conf
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits.
DATE
Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich
2000 — conf
WiCkeD: analog circuit synthesis incorporating mismatch.
CICC
Kurt Antreich, Josef Eckmüller, Helmut Graeb, Michael Pronath, Frank Schenkel, Robert Schwencker, Stephan Zizala
1999 J jnl
Analog testing by characteristic observation inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich
1999 A conf
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints.
DATE
Robert Schwencker, Josef Eckmüller, Helmut E. Graeb, Kurt Antreich
1999 J jnl
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs.
ACM Trans. Design Autom. Electr. Syst.
Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich
1999 J jnl
Simulationsbasierter Testentwurf für gemischt analog-digitale Systeme.
Informationstechnik Tech. Inform.
Michael Pronath, Volker Glöckel, Helmut Gräb, Kurt Antreich
1997 — conf
DFG-Schwerpunktprogramm: Entwurf und Entwurfsmethodik eingebetteter Systeme.
GI Jahrestagung
Kurt Antreich, Franz J. Rammig, Wolfgang Rosenstiel, Detlef Schmid, Klaus Waldschmidt
1997 J jnl
DFG-Schwerpunktprogramm: Entwurf und Entwurfsmethodik eingebetteter Systeme.
Inform. Forsch. Entwickl.
Kurt Antreich, Franz J. Rammig, Wolfgang Rosenstiel, Detlef Schmid, Klaus Waldschmidt
1997 J jnl
Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits.
J. Electron. Test.
Peter A. Krauss, Andreas Ganz, Kurt Antreich
1995 — conf
A formal non-heuristic ATPG approach.
EURO-DAC
Manfred Henftling, Hannes C. Wittmann, Kurt Antreich
1995 A conf
A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization.
ICCAD
Manfred Henftling, Hannes C. Wittmann, Kurt Antreich
1995 A conf
Design based analog testing by Characteristic Observation Inference.
ICCAD
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich
1995 A* conf
Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm.
DAC
Bernd Wurth, Klaus Eckl, Kurt Antreich
1995 A* conf
Logic Clause Analysis for Delay Optimization.
DAC
Bernhard Rohfleisch, Bernd Wurth, Kurt Antreich
1994 — conf
A new power estimation technique with application to decomposition of Boolean functions for low power.
EURO-DAC
Peter H. Schneider, Kurt Antreich, Ulf Schlichtmann
1994 J jnl
Circuit analysis and optimization driven by worst-case distances.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kurt Antreich, Helmut E. Graeb, Claudia U. Wieser
1994 J jnl
Iterative placement improvement by network flow methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Konrad Doll, Frank M. Johannes, Kurt Antreich
1994 C conf
PHIroute: A Parallel Hierarchical Sea-of-Gates Router.
ISCAS
Henning Spruth, Frank M. Johannes, Kurt Antreich
1994 A* conf
Path Hashing to Accelerate Delay Fault Simulation.
DAC
Manfred Henftling, Hannes C. Wittmann, Kurt Antreich
1993 — conf
Application of Fault Parallelism to the Automatic Test Pattern Generation for Sequential Circuits.
Parallel Computer Architectures
Peter A. Krauss, Kurt Antreich
1993 A* conf
Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances.
DAC
Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich
1992 — conf
Design verification considering manufacturing tolerances by using worst-caste distances.
EURO-DAC
Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich
1991 A conf
Circuit Optimization Driven by Worst-Case Distances.
ICCAD
Kurt Antreich, Helmut E. Graeb
1991 J jnl
GORDIAN: VLSI placement by quadratic programming and slicing optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jürgen M. Kleinhans, Georg Sigl, Frank M. Johannes, Kurt Antreich
1990 — conf
An accurate model for ambiguity delay simulation.
EURO-DAC
Thomas H. Krodel, Kurt Antreich
1987 J jnl
Accelerated Fault Simulation and Fault Grading in Combinational Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kurt Antreich, Michael H. Schulz