| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2026 | J | jnl |
IEEE Commun. Lett.
|
| 2026 | J | jnl |
IEEE Trans. Ind. Electron.
|
| 2025 | J | jnl |
IEEE Trans. Ind. Electron.
|
| 2025 | J | jnl |
IEEE Trans. Instrum. Meas.
|
| 2025 | — | conf |
VTC2025-Fall
|
| 2024 | J | jnl |
IEEE Trans. Instrum. Meas.
|
| 2023 | C | conf |
ISCAS
|
| 2022 | J | jnl |
IEEE Trans. Instrum. Meas.
|
| 2020 | J | jnl |
IEEE Access
|
| 2020 | — | conf |
FPGA Realization of Hardware-Flexible Parallel Structure FIR Filters Using Combined Systolic Arrays.
I2MTC
|
| 2019 | — | conf |
I2MTC
|
| 2019 | — | conf |
I2MTC
|
| 2019 | — | conf |
I2MTC
|
| 2019 | J | jnl |
IEICE Electron. Express
|
| 2019 | J | jnl |
J. Circuits Syst. Comput.
|
| 2019 | — | conf |
I2MTC
|
| 2019 | J | jnl |
IEEE Access
|
| 2019 | C | conf |
ISCAS
|
| 2018 | J | jnl |
IEICE Electron. Express
|
| 2018 | J | jnl |
IEICE Electron. Express
|
| 2018 | — | conf |
APCCAS
|
| 2016 | J | jnl |
J. Circuits Syst. Comput.
|
| 2015 | J | jnl |
IEICE Electron. Express
|
| 2014 | J | jnl |
Circuits Syst. Signal Process.
|