Kuo-Liang Cheng

19 papers A* 1A 5Misc 4Journal 4Unranked 5

Year	Rank	Type	Title / Venue / Authors
2007	J	`jnl`	Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu
2007	J	`jnl`	STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. Very Large Scale Integr. Syst. Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
2005	—	`conf`	Design and test of a scalable security processor. ASP-DAC Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2004	A	`conf`	An SOC Test Integration Platform and Its Industrial Realization. ITC Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee
2003	A	`conf`	FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
2003	A	`conf`	Fault Pattern Oriented Defect Diagnosis for Memories. ITC Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
2003	Misc	`conf`	Test and Diagnosis of Word-Oriented Multiport Memories. VTS Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2002	J	`jnl`	Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
2002	—	`conf`	Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
2002	J	`jnl`	Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
2002	Misc	`conf`	RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
2002	—	`conf`	Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
2002	—	`conf`	Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
2001	—	`conf`	Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
2001	Misc	`conf`	Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. VTS Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
2001	A	`conf`	March-based RAM diagnosis algorithms for stuck-at and coupling faults. ITC Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
2001	A*	`conf`	Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
2000	A	`conf`	Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
2000	Misc	`conf`	Simulation-Based Test Algorithm Generation for Random Access Memories. VTS Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu