Kuo-Hsing Cheng

109 papers C 26Journal 30Unranked 52

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A 20 Gb/s Half-Rate PAM-4 Clock and Data Recovery with Data Independent Phase Tracking Compensation Technique. ICECS Kuang-Ya Wu, Kuo-Hsing Cheng, Yu-Yen Ke, Chih-Wei Tsai, Hong-Yi Huang
2025	—	`conf`	A 5 Gb/s Half-Rate Clock and Data Recovery with Adaptive Equalizer Using ISI Detecting Technique. ICECS Yan-Ci Li, Kuo-Hsing Cheng, Shi-Yang Sun, Hong-Yi Huang
2025	C	`conf`	A Reference-less All-digital BPSK-based Clock and Data Recovery Circuitry for Die-to-Die Interfaces. ISCAS Yi-Ting Yang, Hao-Chiao Hong, Kuo-Hsing Cheng
2023	—	`conf`	A 1~50mA 20ns Settling Time Low Dropout Regulator. ICECS Hong-Yi Huang, Yu-Ming Tsao, Angelo Nico M. Daroy, Kuo-Hsing Cheng
2023	—	`conf`	A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System. ICECS Kuo-Hsing Cheng, Chun-Yao Chang, Hong-Yi Huang, Yun-Teng Shih
2021	J	`jnl`	A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications. IEEE Trans. Very Large Scale Integr. Syst. Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng
2019	C	`conf`	A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System. DDECS Tsung-Han Tsai, Po-Ting Chi, Kuo-Hsing Cheng
2018	J	`jnl`	A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection. IEEE Trans. Circuits Syst. I Regul. Pap. Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, Jen-Chieh Liu
2018	C	`conf`	A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application. ISCAS Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng
2018	J	`jnl`	Low supply voltage and multiphase all-digital crystal-less clock generator. IET Circuits Devices Syst. Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Chi-Yang Chang
2017	—	`conf`	A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering. VLSI-DAT Yo-Hao Tu, Kai-Wen Yao, Minghao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, Jia-Shiang Fu
2016	J	`jnl`	A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. IEICE Electron. Express Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu
2016	C	`conf`	A chaotically injected timing technique for ring-based oscillators. DDECS Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang
2016	C	`conf`	Gm-C filter with automatic calibration scheme. DDECS Hong-Yi Huang, Kun-Yuan Chen, Jia-Hao Xie, Ming-Ta Lee, Hao-Chiao Hong, Kuo-Hsing Cheng
2016	C	`conf`	Low-voltage indoor energy harvesting using photovoltaic cell. DDECS Hong-Yi Huang, Shao-Zu Yen, Jhen-Hong Chen, Hao-Chiao Hong, Kuo-Hsing Cheng
2016	J	`jnl`	Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture. IEICE Trans. Electron. Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng
2015	C	`conf`	A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. DDECS Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang
2015	C	`conf`	PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing. DDECS Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching-Hsing Luo, Jin-Chern Chiou
2014	J	`jnl`	A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes. IEEE Trans. Circuits Syst. II Express Briefs Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun
2014	C	`conf`	A 64-MHz∼640-MHz 64-phase clock generator. DDECS Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng
2014	C	`conf`	A low supply voltage synchronous mirror delay with quadrature phase output. DDECS Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang
2013	C	`conf`	A low jitter delay-locked-loop applied for DDR4. DDECS Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang
2013	C	`conf`	External capacitorless low dropout linear regulator using cascode structure. DDECS Hong-Yi Huang, Cheng-Yu Chen, Kuo-Hsing Cheng
2013	C	`conf`	Indoor energy harvesting using photovoltaic cell for battery recharging. DDECS Hong-Yi Huang, Chinet Otic Mocorro, Julyver Pinaso, Kuo-Hsing Cheng
2012	J	`jnl`	A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. IEEE Trans. Circuits Syst. II Express Briefs Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang
2012	J	`jnl`	A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit. IEICE Trans. Electron. Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Yu-Sheng Chen, Pang-Shiu Chen, Ming-Jinn Tsai, Yu-Lung Lo
2012	C	`conf`	A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology. ISCAS Bo-Qian Jiang, Cheng-Liang Hung, Bing-Hung Chen, Kuo-Hsing Cheng
2012	J	`jnl`	An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing. IEEE Trans. Very Large Scale Integr. Syst. Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, Bo-Qian Jiang
2012	C	`conf`	Auto-calibration techniques in built-in jitter measurement circuit. DDECS Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng
2011	—	`conf`	A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation. ESSCIRC Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-hao Fan, Chi-Yang Chang
2011	J	`jnl`	A 0.5-V 0.4-2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip. IEEE Trans. Circuits Syst. I Regul. Pap. Kuo-Hsing Cheng, Yu-Chang Tsai, Yu-Lung Lo, Jing-Shiuan Huang
2011	J	`jnl`	A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique. IEEE J. Solid State Circuits Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang
2011	—	`conf`	A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. ISSCC Shyh-Shyuan Sheu, Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai
2011	J	`jnl`	A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. IEEE Trans. Circuits Syst. II Express Briefs Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu
2011	J	`jnl`	A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit. IEEE Trans. Very Large Scale Integr. Syst. Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu
2011	C	`conf`	All digital phase-locked loop using active inductor oscillator and novel locking algorithm. ISCAS Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo
2011	J	`jnl`	Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, Kai-Wei Hong
2011	J	`jnl`	Fast-Write Resistive RAM (RRAM) for Embedded Applications. IEEE Des. Test Comput. Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Meng-Fan Chang, Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Frederick T. Chen, Ming-Jinn Tsai
2010	—	`conf`	A 3 GHz DLL-based clock generator with stuck locking protection. ICECS Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng
2010	J	`jnl`	A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications. IEEE Trans. Circuits Syst. II Express Briefs Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, Ying-Fu Lin
2010	—	`conf`	A CMOS adaptive equalizer using low-voltage zero generators technique. ESSCIRC Yu-Chang Tsai, Kuo-Hsing Cheng, Yen-Hsueh Wu, Ying-Fu Lin
2010	—	`conf`	A loading effect insensitive and high precision clock synchronization circuit. ESSCIRC Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu, Chien-Cheng Chen
2010	C	`conf`	A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. DDECS Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang
2009	C	`conf`	0.5V 160-MHz 260uW all digital phase-locked loop. DDECS Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng
2009	J	`jnl`	A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver. IEEE Trans. Very Large Scale Integr. Syst. Shu-Yu Jiang, Kuo-Hsing Cheng, Pei-Yi Jian
2009	J	`jnl`	A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. IEICE Trans. Electron. Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo
2009	J	`jnl`	Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. IEEE Trans. Circuits Syst. II Express Briefs Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng
2009	—	`conf`	Designing ultra-low voltage PLL Using a bulk-driven technique. ESSCIRC Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng
2009	J	`jnl`	High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. IEICE Trans. Electron. Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng
2009	J	`jnl`	Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shu-Yu Jiang, Chan-Wei Huang, Yu-Lung Lo, Kuo-Hsing Cheng
2008	—	`conf`	A 1-V 10-bit 2GSample/s D/A converter based on precision current reference in 90-nm CMOS. ICECS Kuo-Hsing Cheng, Hsin-Hao Wang, Ding-Jyun Huang
2008	J	`jnl`	A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation. IEEE J. Solid State Circuits Kuo-Hsing Cheng, Chia-Wei Su, Kai-Fei Chang
2008	C	`conf`	A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw
2008	—	`conf`	A compact and low-power SRAM with improved read static noise margin. ICECS Cihun-Siyong Alex Gong, Ci-Tong Hong, Kai-Wen Yao, Muh-Tian Shiue, Kuo-Hsing Cheng
2008	—	`conf`	A high-accuracy and high-efficiency on-chip current sensing for current-mode control CMOS DC-DC buck converter. ICECS Kuo-Hsing Cheng, Chia-Wei Su, Hsin-Hsin Ko
2008	—	`conf`	A low jitter self-calibration PLL for 10Gbps SoC transmission links application. ICECS Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu
2008	—	`conf`	A wide-range DLL-based clock generator with phase error calibration. ICECS Kuo-Hsing Cheng, Chia-Wei Su, Meng-Jhe Wu, Yu-Ling Chang
2008	J	`jnl`	Highly Accurate and Efficient Current-Mode PWM CMOS DC-DC Buck Converter with On-Chip Current-Sensing. IEICE Trans. Electron. Kuo-Hsing Cheng, Chia-Wei Su, Hsin-Hsin Ko
2007	—	`conf`	A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique. ICECS Kuo-Hsing Cheng, Yu-Lung Lo, Ching-Wen Lai, Wei-Bin Yang
2007	J	`jnl`	A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator. IEEE Trans. Circuits Syst. II Express Briefs Kuo-Hsing Cheng, Yu-Lung Lo
2007	—	`conf`	A Phase Interpolator For Sub-1V And High Frequency For Clock And Data Recovery. ICECS Kuo-Hsing Cheng, Pei-Kai Tseng, Yu-Lung Lo
2007	C	`conf`	A Sub-1V Low-Power High-Speed Static Frequency Divider. ISCAS Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su
2007	—	`conf`	All-Digital PLL Using Pulse-Based DCO. ICECS Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng
2006	J	`jnl`	64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics. J. Circuits Syst. Comput. Kuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee
2006	C	`conf`	A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. ISCAS Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng
2006	—	`conf`	A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay. ICECS Kai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang
2006	—	`conf`	A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. DATE Designers' Forum Kuo-Hsing Cheng, Yu-Lung Lo
2006	—	`conf`	Design of Self-Sampling Based ASK Demodulator for Implantable Microsystem. ICECS Cihun-Siyong Alex Gong, Chen-Lung Wu, Sheng-Yang Ho, Tong-Yi Chen, Jia-Chun Huang, Chia-Wei Su, Chun-Hsien Su, Yin Chang, Kuo-Hsing Cheng, Yu-Lung Lo, Muh-Tian Shiue
2006	J	`jnl`	Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications. J. Inf. Sci. Eng. Kuo-Hsing Cheng, Shun-Wen Cheng
2006	C	`conf`	Self-sampled vernier delay line for built-in clock jitter measurement. ISCAS Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang
2005	J	`jnl`	64-Bit High-Performance Power-Aware Conditional Carry Adder Design. IEICE Trans. Electron. Kuo-Hsing Cheng, Shun-Wen Cheng
2005	—	`conf`	A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ISCAS (2) Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang
2005	—	`conf`	A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. ESSCIRC Kuo-Hsing Cheng, Yu-Lung Lo
2005	—	`conf`	A phase-detect synchronous mirror delay for clock skew-compensation circuits. ISCAS (2) Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo, Chia-Wei Su
2005	—	`conf`	The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. ECCTD Wei-Bin Yang, Shu-Chang Kuo, Yuan-Hua Chu, Kuo-Hsing Cheng
2004	—	`conf`	64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. IWSOC Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang
2004	—	`conf`	64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. ISVLSI Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao
2004	—	`conf`	A 14-bit, 200 MS/s digital-to-analog converter without trimming. ISCAS (1) Kuo-Hsing Cheng, Tsung-Shen Chen, Chia Ming Tu
2004	—	`conf`	A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. ISCAS (1) Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo
2004	—	`conf`	A fast-lock DLL with power-on reset circuit. ISCAS (4) Kuo-Hsing Cheng, Yu-Lung Lo
2004	—	`conf`	Static divided word matching line for low-power Content Addressable Memory design. ISCAS (2) Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang
2003	—	`conf`	A CMOS charge pump for sub-2.0 V operation. ISCAS (5) Kuo-Hsing Cheng, Chung-Yu Chang, Chia-Hung Wei
2003	—	`conf`	A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. IWSOC Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu, Shu-Yin Hung
2003	—	`conf`	A Robust Handshake for Asynchronous System. IWSOC Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu
2003	—	`conf`	A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application. ISCAS (5) Kuo-Hsing Cheng, Yung-Hsiang Lin
2003	J	`jnl`	A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop. IEEE Trans. Circuits Syst. II Express Briefs Kuo-Hsing Cheng, Wei-Bin Yang, Cheng-Ming Ying
2003	—	`conf`	A mixed-mode delay-locked loop for wide-range operation and multiphase outputs. ISCAS (2) Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu
2003	—	`conf`	A new robust handshake for asymmetric asynchronous micro-pipelines. ISCAS (5) Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang
2003	—	`conf`	BIST for clock jitter measurements. ISCAS (5) Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen
2002	—	`conf`	Influences of minimum cut plane properties on the mincut circuit partitioning problems. ICECS Kuo-Hsing Cheng, Shun-Wen Cheng
2002	—	`conf`	Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. ASP-DAC/VLSI Design Kuo-Hsing Cheng, Shun-Wen Cheng
2001	—	`conf`	A 1.2 V 500 MHz 32-bit carry-lookahead adder. ICECS Kuo-Hsing Cheng, Wen-Shiuan Lee, Yung-Chong Huang
2001	—	`conf`	A CMOS low power voltage controlled oscillator with split-path controller. ICECS Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, Shyh-Shyuan Sheu
2001	—	`conf`	A difference detector PFD for low jitter PLL. ICECS Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang, Wei-Bin Yang
2001	—	`conf`	A low-power high driving ability voltage control oscillator used in PLL. ISCAS (4) Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung
2001	—	`conf`	A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning. ICECS Kuo-Hsing Cheng, Shun-Wen Cheng
2001	—	`conf`	Accurate current mirror with high output impedance. ICECS Kuo-Hsing Cheng, Chi-Che Chen, Chun-Fu Chung
2001	—	`conf`	ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning. ISCAS (5) Shun-Wen Cheng, Kuo-Hsing Cheng
2000	C	`conf`	The design and implementation of DCT/IDCT chip with novel architecture. ISCAS Kuo-Hsing Cheng, Chih-Sheng Huang, Chun-Pin Lin
1999	—	`ch.`	Dynamic Random Access Memory. The VLSI Handbook Kuo-Hsing Cheng
1999	—	`conf`	The novel efficient design of XOR/XNOR function for adder applications. ICECS Kuo-Hsing Cheng, Chih-Sheng Huang
1999	—	`conf`	The suggestion for CFS CMOS buffer. ICECS Kuo-Hsing Cheng, Wei-Bin Yang
1998	—	`conf`	Low voltage low power high-speed BiCMOS multiplier. ICECS Kuo-Hsing Cheng, Yu-Kwang Yeha, Farn-Sou Lian
1996	—	`conf`	A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic. ICECS Kuo-Hsing Cheng, Yu-Yee Liow
1995	C	`conf`	A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications. ISCAS Chung-Yu Wu, Jr-Houng Lu, Kuo-Hsing Cheng
1995	C	`conf`	Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu
1994	C	`conf`	Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit. ISCAS Yuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu
1993	J	`jnl`	Analysis and design of a new race-free four-phase CMOS logic. IEEE J. Solid State Circuits Chung-Yu Wu, Kuo-Hsing Cheng, Jinn-Shyan Wang
1991	J	`jnl`	Latched CMOS differential logic (LCDL) for complex high-speed VLSI. IEEE J. Solid State Circuits Chung-Yu Wu, Kuo-Hsing Cheng