Kunihiro Fujiyoshi

46 papers A 2B 1C 7Journal 21Unranked 15
YearRankTypeTitle / Venue / Authors
2025 C conf
A Method for Selecting the Wiring Direction from Terminals using a Planar Graph Drawing Method.
ISCAS
Takuto Amari, Heihachirou Hasumi, Kunihiro Fujiyoshi
2025 J jnl
Fault-Tolerant Routing in Bicubes.
IEICE Trans. Inf. Syst.
Yitong Wang, Htoo Htoo Sandi Kyaw, Kunihiro Fujiyoshi, Keiichi Kaneko
2025 J jnl
Polygon Fracture Method Considering Maximum Shot Size for Variable Shaped-beam Mask Writing.
IPSJ Trans. Syst. LSI Des. Methodol.
Mitsuru Hasegawa, Taiki Matsuzaki, Kunihiro Fujiyoshi
2024 — conf
An improved method for a set-pair routing problem by SAT.
APCCAS
Koki Nagakura, Kunihiro Fujiyoshi
2024 J jnl
Node-to-Node and Node-to-Set Disjoint Paths Problems in Bicubes.
IEICE Trans. Inf. Syst.
Arata Kaneko, Htoo Htoo Sandi Kyaw, Kunihiro Fujiyoshi, Keiichi Kaneko
2023 — conf
A Necessary and Sufficient Condition to Generate Representative Clip for Edge-Constrained Clustering of Layout Pattern Classification Problem.
NEWCAS
Kunihiro Fujiyoshi, Tomoya Masutani
2017 J jnl
Photo-Diode Array Partitioning Problem for a Rectangular Region.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kunihiro Fujiyoshi, Takahisa Imano
2016 — conf
A method for photo-diode array partitioning problem.
MWSCAS
Kunihiro Fujiyoshi, Takahisa Imano
2014 J jnl
A Method of Analog IC Placement with Common Centroid Constraints.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keitaro Ue, Kunihiro Fujiyoshi
2014 — conf
Adjacent common centroid placement for analog IC layout design.
APCCAS
Kenichiro Murotatsu, Kunihiro Fujiyoshi
2014 — conf
Average placement method with common centroid constraints for analog IC layout design.
MWSCAS
Kunihiro Fujiyoshi, Keitaro Ue
2012 — conf
An efficient solution space for floorplan of 3D-LSI.
ICECS
Hiroshi Tezuka, Kunihiro Fujiyoshi
2011 C conf
A novel representation for repeated placement.
ISCAS
Kunihiro Fujiyoshi, Keisuke Ishihara, Tan Wei Liang
2010 J jnl
On the Number of Rooms in a Rectangular Solid Dissection.
Inf. Media Technol.
Hidenori Ohta, Toshinori Yamada, Kunihiro Fujiyoshi
2010 J jnl
On the Number of Rooms in a Rectangular Solid Dissection.
J. Inf. Process.
Hidenori Ohta, Toshinori Yamada, Kunihiro Fujiyoshi
2009 J jnl
A Tree Based Novel Representation for 3D-Block Packing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara
2009 J jnl
Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Natsumi Hirakawa, Kunihiro Fujiyoshi
2009 C conf
Representation of 3D-LSI Floorplan based on Stacked-rectangular-dissection.
ISCAS
Hidenori Ohta, Kunihiro Fujiyoshi
2008 J jnl
The O-Sequence: Representation of 3D-Dissection.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hidenori Ohta, Toshinori Yamada, Chikaaki Kodama, Kunihiro Fujiyoshi
2007 J jnl
A fast algorithm for rectilinear block packing based on selected sequence-pair.
Integr.
Kunihiro Fujiyoshi, Chikaaki Kodama, Akira Ikeda
2007 C conf
DTS: A Tree Based Representation for 3D-Block Packing.
ISCAS
Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara
2007 J jnl
Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shinichi Koda, Chikaaki Kodama, Kunihiro Fujiyoshi
2006 C conf
Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems.
ISCAS
Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi
2006 — conf
Improved method of cell placement with symmetry constraints for analog IC layout design.
ISPD
Shinichi Kouda, Chikaaki Kodama, Kunihiro Fujiyoshi
2006 — conf
Thermal Driven Module Placement Using Sequence-pair.
APCCAS
Norihide Okada, Chikaaki Kodama, Takashi Sato, Kunihiro Fujiyoshi
2005 J jnl
A Graph Based Soft Module Handling in Floorplan.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroaki Itoga, Chikaaki Kodama, Kunihiro Fujiyoshi
2005 J jnl
Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge.
IEICE Trans. Inf. Syst.
Chikaaki Kodama, Kunihiro Fujiyoshi
2004 — conf
A novel encoding method into sequence-pair.
ISCAS (5)
Chikaaki Kodama, Kunihiro Fujiyoshi, Teppei Koga
2003 J jnl
An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuya Wakata, Hiroaki Saito, Kunihiro Fujiyoshi, Keishi Sakanushi, Takayuki Obata, Chikaaki Kodama
2003 — conf
Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair.
ASP-DAC
Chikaaki Kodama, Kunihiro Fujiyoshi
2002 J jnl
An Efficient Decoding Method of Sequence-Pair with Reduced Redundancy.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chikaaki Kodama, Kunihiro Fujiyoshi
2002 — conf
An efficient decoding method of sequence-pair.
APCCAS (2)
Chikaaki Kodama, Kunihiro Fujiyoshi
2002 — conf
An improved method of convex-shaped block packing based on sequence-pair [VLSI layout].
APCCAS (2)
Hiroaki Saito, Kazuya Wakata, Kunihiro Fujiyoshi, Keishi Sakanushi, Takayuki Obata
2000 J jnl
Arbitrary convex and concave rectilinear block packing usingsequence-pair.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kunihiro Fujiyoshi, Hiroshi Murata
2000 C conf
Simulated annealing search through general structure floorplans using sequence-pair.
ISCAS
Koji Kiyota, Kunihiro Fujiyoshi
1999 — conf
Arbitrary convex and concave rectilinear block packing using sequence-pair.
ISPD
Kunihiro Fujiyoshi, Hiroshi Murata
1998 J jnl
Module packing based on the BSG-structure and IC layout applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
1998 J jnl
VLSI/PCB placement with obstacles based on sequence pair.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko
1997 — conf
A mapping from sequence-pair to rectangular dissection.
ASP-DAC
Hiroshi Murata, Kunihiro Fujiyoshi, Tomomi Watanabe, Yoji Kajitani
1997 J jnl
Design of minimum and uniform bipartites for optimum connection blocks of FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
1997 — conf
VLSI/PCB placement with obstacles based on sequence-pair.
ISPD
Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko
1996 A conf
Module placement on BSG-structure and IC layout applications.
ICCAD
Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
1996 J jnl
VLSI module placement based on rectangle-packing by the sequence-pair.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
1995 A conf
Rectangle-packing-based module placement.
ICCAD
Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
1994 C conf
Design of Optimum Totally Perfect Connection-Blocks of FPGA.
ISCAS
Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
1994 B conf
The Totally-Perfect Bipartite Graph and Its Construction.
ISAAC
Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu