Kunihiro Asada

207 papers A 10B 4C 15Journal 72Unranked 106

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. IEICE Trans. Electron. Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada
2021	—	`conf`	Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper. ICICDT Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Kunihiro Asada
2019	J	`jnl`	A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
2019	J	`jnl`	Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. Daigo Takahashi, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada
2019	J	`jnl`	Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada
2018	—	`conf`	A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2018	—	`conf`	A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. MWSCAS Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
2018	C	`conf`	A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2018	J	`jnl`	Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2018	J	`jnl`	Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. IEEE Trans. Instrum. Meas. Nguyen Ngoc Mai Khanh, Shigeru Nakajima, Tetsuya Iizuka, Yoshio Mita, Kunihiro Asada
2018	J	`jnl`	Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2018	J	`jnl`	Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada
2018	J	`jnl`	Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda
2018	J	`jnl`	Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	J	`jnl`	A CMOS Broadband Transceiver with On-Chip Antenna Array and Built-In Pulse-Delay Calibration for Millimeter-Wave Imaging Applications. IEICE Trans. Electron. Nguyen Ngoc Mai Khanh, Kunihiro Asada
2017	J	`jnl`	A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	J	`jnl`	A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. IEEE SENSORS Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada
2017	—	`conf`	A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	—	`conf`	CMOS-on-quartz pulse generator for low power applications. ASP-DAC Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	J	`jnl`	Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	B	`conf`	Extension of power supply impedance emulation method on ATE for multiple power domain. ETS Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2017	—	`conf`	High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2017	—	`conf`	Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2016	—	`conf`	A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada
2016	—	`conf`	A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators. NEWCAS James S. Tandon, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada
2016	—	`conf`	A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada
2016	J	`jnl`	An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2016	J	`jnl`	An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface. IEICE Trans. Electron. Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada
2016	—	`conf`	Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise. ISQED Masahiro Kano, Toru Nakura, Kunihiro Asada
2016	A	`conf`	Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2016	J	`jnl`	Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. J. Electron. Test. Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
2016	—	`conf`	Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. ICECS Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
2016	—	`conf`	Fully automated PLL compiler generating final GDS from specification. ISQED Toru Nakura, Kunihiro Asada
2016	—	`conf`	One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise. EWME Toru Nakura, Yuki Okamoto, Yoshio Mita, Kunihiro Asada
2016	J	`jnl`	Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. IEICE Trans. Electron. Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
2016	A	`conf`	Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2016	—	`conf`	Resonant power supply noise reduction using a triangular active charge injection. ICECS Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2015	J	`jnl`	A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs. IEEE Trans. Instrum. Meas. Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada
2015	—	`conf`	A Technique for Analyzing On-Chip Power Supply Impedance. ATS Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada
2015	—	`conf`	A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2015	C	`conf`	An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2015	J	`jnl`	Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline. IEICE Electron. Express Toru Nakura, Hiroaki Matsui, Kunihiro Asada
2015	J	`jnl`	Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer. IEICE Trans. Electron. Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Atsunori Hattori, Kunihiro Asada
2015	—	`conf`	Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2014	J	`jnl`	A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada
2014	—	`conf`	A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. ATS Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada
2014	J	`jnl`	A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2014	C	`conf`	A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. ISCAS James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada
2014	—	`conf`	A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique. ICECS Hongbo Zhu, Kunihiro Asada
2014	C	`conf`	Burst-pulse Generator based on transmission line toward sub-MMW. DDECS Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada
2014	B	`conf`	High-resolution measurement of magnetic field generated from cryptographic LSIs. SAS Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada
2014	C	`conf`	Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. DDECS Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada
2014	A	`conf`	Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. ITC Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada
2014	—	`conf`	Streaming distribution of a live seminar: Rudimentary knowledge for LSI design. EWME Toru Nakura, Kunihiro Asada
2013	—	`conf`	A Pulse Width controlled PLL and its automated design flow. ICECS Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2013	A	`conf`	A novel test structure for measuring the threshold voltage variance in MOSFETs. ITC Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada
2013	—	`conf`	A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. CICC James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada
2013	—	`conf`	A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2013	—	`conf`	A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. CICC Tetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, Kunihiro Asada
2013	—	`conf`	An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada
2013	J	`jnl`	High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2013	—	`conf`	High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
2013	—	`conf`	Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator. ICECS Tomohiko Yano, Toru Nakura, Kunihiro Asada
2013	J	`jnl`	On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. IEICE Trans. Electron. Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2013	J	`jnl`	Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments. IEICE Trans. Electron. Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
2012	—	`conf`	7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada
2012	J	`jnl`	A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. IEICE Trans. Electron. Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada
2012	—	`conf`	A New Procedure for Measuring High-Accuracy Probability Density Functions. Asian Test Symposium Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira
2012	—	`conf`	A design-for-test apparatus for measuring on-chip temperature with fine granularity. ISQED James S. Tandon, Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada
2012	J	`jnl`	All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. IEICE Trans. Electron. Tetsuya Iizuka, Kunihiro Asada
2012	J	`jnl`	All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada
2012	J	`jnl`	All-digital tunable power amplifier consuming 0.03mW/MHz using 0.18µm CMOS. IEICE Electron. Express Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada
2012	J	`jnl`	Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling. IEICE Trans. Electron. Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
2012	J	`jnl`	Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2012	—	`conf`	Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation. COOL Chips Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
2012	—	`conf`	Impact of All-Digital PLL on SoC Testing. Asian Test Symposium Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
2012	J	`jnl`	Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. IEICE Trans. Electron. Toru Nakura, Kunihiro Asada
2012	J	`jnl`	On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Trans. Electron. Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2012	A	`conf`	Power integrity control of ATE for emulating power supply fluctuations on customer environment. ITC Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
2012	—	`conf`	Range extension of inductive coupling communication using multi-stage resonance. ISCIT Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada
2012	—	`conf`	Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes. ASYNC Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	A 0.18-µm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability. IEICE Trans. Electron. Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada
2011	J	`jnl`	A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging. IEICE Trans. Electron. Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada
2011	J	`jnl`	A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. IEEE J. Solid State Circuits Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada
2011	J	`jnl`	A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Salih Ergün, Ülkühan Güler, Kunihiro Asada
2011	—	`conf`	A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS. ASP-DAC Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada
2011	—	`conf`	A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. ASP-DAC Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. ESSCIRC Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada
2011	J	`jnl`	All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS. ICECS Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	All-digital ramp waveform generator for two-step single-slope ADC. IEICE Electron. Express Tetsuya Iizuka, Kunihiro Asada
2011	C	`conf`	An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. DDECS Tetsuya Iizuka, Kunihiro Asada
2011	C	`conf`	An equivalent-time and clocked approach for continuous-time quantization. ISCAS Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada
2011	A	`conf`	Application of a continuous-time level crossing quantization method for timing noise measurements. ITC Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu
2011	J	`jnl`	Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2011	C	`conf`	Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011	A	`conf`	Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. ISLPED Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system. ICECS Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology. ICECS Mohamed Abbas, Takahiro J. Yamaguchi, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada
2011	J	`jnl`	On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Trans. Electron. Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy. ISOCC Teruki Nakasato, Toru Nakura, Kunihiro Asada
2011	J	`jnl`	Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation. J. Next Gener. Inf. Technol. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method. IEICE Trans. Electron. Shingo Mandai, Taihei Momma, Makoto Ikeda, Kunihiro Asada
2010	—	`conf`	A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary. ISSCC Shingo Mandai, Makoto Ikeda, Kunihiro Asada
2010	J	`jnl`	A 8bit two stage time-to-digital converter using time difference amplifier. IEICE Electron. Express Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2010	J	`jnl`	A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2010	—	`conf`	All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. ESSCIRC Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2010	A	`conf`	An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. DATE Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada
2010	C	`conf`	Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
2010	—	`conf`	Cascaded time difference amplifier using differential logic delay cell. ASP-DAC Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2010	—	`conf`	Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging. DFT Kunihiro Asada, Makoto Ikeda, Benjamin Stefan Devlin, Taku Sogabe
2010	J	`jnl`	Time Difference Amplifier with Robust Gain Using Closed-Loop Control. IEICE Trans. Electron. Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada
2010	—	`conf`	Time-to-digital converter based on time difference amplifier with non-linearity calibration. ESSCIRC Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009	—	`conf`	647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. ESSCIRC Benjamin Stefan Devlin, MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009	C	`conf`	All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009	—	`conf`	Circuit design using stripe-shaped PMELA TFTs on glass. ASP-DAC Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada
2009	J	`jnl`	Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. IEICE Trans. Electron. Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009	C	`conf`	Measurement of power supply noise tolerance of self-timed processor. DDECS Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda
2009	—	`conf`	Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. ACM Great Lakes Symposium on VLSI MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2009	—	`conf`	SAT-based ATPG testing of inter- and intra-gate bridging faults. ECCTD Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada
2009	B	`conf`	Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. ETS Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada
2007	—	`conf`	3.5-Gb/s extended frequency range wave-pipeline PRBS Generator in 0.18-μm CMOS. ICECS Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada
2007	C	`conf`	Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology. DDECS Zhicheng Liang, Makoto Ikeda, Kunihiro Asada
2007	—	`conf`	Datapath Delay Distributions for Data/Instruction against PVT Variations in 90nm CMOS. ICECS Makoto Ikeda, Ken Ishii, Taku Sogabe, Kunihiro Asada
2007	—	`conf`	Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. ASP-DAC Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada
2007	—	`conf`	FPGA-Based 3-D engine for high-speed 3-D measurement based on light-section method. FPT Yusuke Yachide, Makoto Ikeda, Kunihiro Asada
2007	—	`conf`	LAGS System Using Data/Instruction Grain Power Control. ISSCC Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada
2007	—	`conf`	OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. ISQED Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2007	—	`conf`	Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS. ICECS Kenichiro Kurihara, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2007	J	`jnl`	Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. IEEE Trans. Very Large Scale Integr. Syst. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2007	—	`conf`	VLSI CAD Education and Exercise Course with Public Domain Tools. MSE Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada
2006	—	`conf`	4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS. ICECS Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada
2006	J	`jnl`	A Structural Approach for Transistor Circuit Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada
2006	J	`jnl`	Autonomous IEICE Trans. Electron. Toru Nakura, Makoto Ikeda, Kunihiro Asada
2006	—	`conf`	Exact Minimum Logic Factoring via Quantified Boolean Satisfiability. ICECS Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada
2006	C	`conf`	Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. ISCAS Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2006	J	`jnl`	Feedforward Active Substrate Noise Cancelling Based on IEICE Trans. Electron. Toru Nakura, Makoto Ikeda, Kunihiro Asada
2006	—	`conf`	High-Speed 3-D Measurement System Using Smart Image Sensor and FPGA Based 3-D Engine. ICECS Yusuke Yachide, Makoto Ikeda, Kunihiro Asada
2006	J	`jnl`	LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taisuke Kazama, Makoto Ikeda, Kunihiro Asada
2006	J	`jnl`	Noise Immunity Investigation of Low Power Design Schemes. IEICE Trans. Electron. Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
2006	J	`jnl`	On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function. IEICE Trans. Electron. Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
2006	A	`conf`	On-chip 8GHz non-periodic high-swing noise detector. DATE Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
2006	—	`conf`	Pre-conditioning Free Footless DCVSL for High-performance Datapaths. ICECS Makoto Ikeda, Kin Hooi Dia, Kunihiro Asada
2006	C	`conf`	Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. DDECS Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
2006	—	`conf`	Tamper Resistivity Analysis for Nano-meter LSI with Process Variations. ICECS Makoto Ikeda, Hiroshi Yamauchi, Kunihiro Asada
2006	—	`conf`	Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement. ICECS Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2006	A	`conf`	Timing-driven cell layout de-compaction for yield optimization by critical area minimization. DATE Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	A 375 × 365 high-speed 3-D range-finding image sensor using row-parallel search architecture and multisampling technique. IEEE J. Solid State Circuits Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells. IEICE Trans. Inf. Syst. Ulkuhan Ekinciel, Hiroaki Yamaoka, Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada
2005	—	`conf`	An algebraic approach for transistor circuit synthesis. ICECS Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada
2005	—	`conf`	Analysis of low noise three-phase asynchronous data transmission. ESSCIRC Nan Li, Makoto Ikeda, Kunihiro Asada
2005	—	`conf`	Autonomous di/dt noise control scheme for margin aware operation. ESSCIRC Toru Nakura, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2005	—	`conf`	Exact minimum-width transistor placement without dual constraint for CMOS cells. ACM Great Lakes Symposium on VLSI Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	On-chip IEICE Trans. Electron. Toru Nakura, Makoto Ikeda, Kunihiro Asada
2005	—	`conf`	On-chip non-periodic high-swing noise detector. ICECS Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs. IEICE Trans. Electron. Toru Nakura, Makoto Ikeda, Kunihiro Asada
2005	—	`conf`	Real-time 3-D measurement system based on light-section method using smart image sensor. ICIP (3) Yusuke Yachide, Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	Stub vs. Capacitor for Power Supply Noise Reduction. IEICE Trans. Electron. Toru Nakura, Makoto Ikeda, Kunihiro Asada
2005	J	`jnl`	Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2004	J	`jnl`	A 120×110 position sensor with the capability of sensitive and selective light detection in wide dynamic range for robust active range finding. IEEE J. Solid State Circuits Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2004	J	`jnl`	A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture. IEEE J. Solid State Circuits Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2004	—	`conf`	A word-parallel digital associative engine with wide search range based on Manhattan distance. CICC Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2004	J	`jnl`	Design and implementation of real-time 3-D image sensor with 640 × 480 pixel resolution. IEEE J. Solid State Circuits Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2004	—	`conf`	Design of real-time VGA 3-D image sensor using mixed-signal techniques. ASP-DAC Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2004	—	`conf`	Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. ISQED Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2004	—	`conf`	High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. ASP-DAC Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2004	—	`conf`	Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime. DFT Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
2004	J	`jnl`	Smart Access Image Sensors for High-Speed and High-Resolution 3-D Measurement based on Light-Section Method. Intell. Autom. Soft Comput. Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2003	—	`conf`	A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architecture. CICC Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2003	—	`conf`	A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design. ESSCIRC Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
2003	—	`conf`	A smart image sensor with high-speed feeble ID-beacon detection for augmented reality system. ESSCIRC Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2003	—	`conf`	Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada
2003	—	`conf`	High-speed position detector using new row-parallel architecture for fast collision prevention system. ISCAS (4) Yusuke Oike, Makoto Ikeda, Kunihiro Asada
2003	—	`conf`	Theoretical study of stubs for power line noise reduction [LSI applications]. CICC Toru Nakura, Makoto Ikeda, Kunihiro Asada
2002	—	`conf`	An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. ASP-DAC/VLSI Design Tohru Ishihara, Kunihiro Asada
2002	—	`conf`	Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. ASP-DAC/VLSI Design Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
2002	—	`conf`	Logic synthesis for PLA with 2-input logic elements. ISCAS (3) Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
2002	—	`conf`	Quick power supply noise estimation using hierarchically derived transfer functions. ICECS Satoshi Sugiyama, Makoto Ikeda, Kunihiro Asada
2001	—	`conf`	A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. ASP-DAC Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
2001	—	`conf`	A smart position sensor for 3-D measurement. ASP-DAC Tomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada
2001	—	`conf`	A system level memory power optimization technique using multiple supply and threshold voltages. ASP-DAC Tohru Ishihara, Kunihiro Asada
2001	—	`conf`	Computational Cost Reduction in Extracting Inductance. ISQED Yusuke Nakashima, Makoto Ikeda, Kunihiro Asada
2001	—	`conf`	Finding an optimal functional decomposition for LUT-based FPGA synthesis. ASP-DAC Jian Qiao, Makoto Ikeda, Kunihiro Asada
2000	J	`jnl`	A Binary Image Sensor for Motion Detection. J. Robotics Mechatronics Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada
2000	—	`conf`	A binary image sensor with flexible motion vector detection using block matching method. ASP-DAC Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada
2000	—	`conf`	DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path. ISQED Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada
2000	B	`conf`	Optimum Functional Decomposition for LUT-Based FPGA Synthesis. FPL Jian Qiao, Makoto Ikeda, Kunihiro Asada
1999	—	`conf`	Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. Great Lakes Symposium on VLSI Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
1999	—	`conf`	Standard design flows of Logic LSIs in Japanese universities and VDEC. MSE Makoto Ikeda, Kunihiro Asada
1998	—	`conf`	An Analysis on VLSI Interconnection Considering Skin Effect. ASP-DAC Tetsuhisa Mido, Kunihiro Asada
1998	—	`conf`	Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. ASP-DAC Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
1998	J	`jnl`	One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects. VLSI Design Rimon Ikeno, Hiroshi Ito, Kunihiro Asada
1997	—	`conf`	Crosstalk noise in high density and high speed interconnections due to inductive coupling. ASP-DAC Tetsuhisa Mido, Kunihiro Asada
1995	C	`conf`	Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54X54 Bit Multiplier. ISCAS Minkyu Song, Kunihiro Asada
1994	—	`conf`	A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs. EDAC-ETC-EUROASIC Makoto Ikeda, Kunihiro Asada
1993	J	`jnl`	Low-power 1/2 frequency dividers using 0.1- mu m CMOS circuits built with ultrathin SIMOX substrates. IEEE J. Solid State Circuits Minoru Fujishima, Kunihiro Asada, Yasuhisa Omura, Katsutoshi Izumi
1992	—	`conf`	A general and efficient mask pattern generator for non-series-parallel CMOS transistor network. Synthesis for Control Dominated Circuits H. Zhang, Kunihiro Asada
1991	J	`jnl`	Evaluation of delay-time degradation of low-voltage BiCMOS based on a novel analytical delay-time modeling. IEEE J. Solid State Circuits Minoru Fujishima, Kunihiro Asada, Takuo Sugano