Kunihiko Iizuka

25 papers Journal 16Unranked 9

Year	Rank	Type	Title / Venue / Authors
2016	—	`conf`	28.3 CMOS biosensor IC focusing on dielectric relaxations of biological water with 120GHz and 60GHz oscillator arrays. ISSCC Takeshi Mitsunaka, Nobuyuki Ashida, Akira Saito, Kunihiko Iizuka, Tetsuhito Suzuki, Yuichi Ogawa, Minoru Fujishima
2016	J	`jnl`	An Analog Front-End for a Multifunction Sensor Employing a Weak-Inversion Biasing Technique With 26 nVrms, 25 aCrms, and 19 fArms Input-Referred Noise. IEEE J. Solid State Circuits Masahiko Maruyama, Shigenari Taguchi, Masafumi Yamanoue, Kunihiko Iizuka
2016	J	`jnl`	CMOS Biosensor IC Focusing on Dielectric Relaxations of Biological Water With 120 and 60 GHz Oscillator Arrays. IEEE J. Solid State Circuits Takeshi Mitsunaka, Daiki Sato, Nobuyuki Ashida, Akira Saito, Kunihiko Iizuka, Tetsuhito Suzuki, Yuichi Ogawa, Minoru Fujishima
2015	J	`jnl`	97-mW 8-Phase CMOS VCO and Dividers for a 134-GHz PLL Synthesizer. IEICE Trans. Electron. Takeshi Mitsunaka, Kunihiko Iizuka, Minoru Fujishima
2015	—	`conf`	A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noise. A-SSCC Masahiko Maruyama, Shigenari Taguchi, Masafumi Yamanoue, Kunihiko Iizuka
2014	J	`jnl`	8-GHz Locking Range and 0.4-pJ Low-Energy Differential Dual-Modulus 10/11 Prescaler. IEICE Trans. Electron. Takeshi Mitsunaka, Masafumi Yamanoue, Kunihiko Iizuka, Minoru Fujishima
2014	J	`jnl`	9dB NF and +11dBm OIP3 CMOS Single Conversion Front-End for a Satellite Low-Noise Block Down-Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Mitsunaka, Yusuke Kishino, Masafumi Yamanoue, Kunihiko Iizuka, Minoru Fujishima
2011	J	`jnl`	Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing. IEEE J. Solid State Circuits Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai
2010	—	`conf`	Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing. ISSCC Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai
2010	J	`jnl`	Foreword. IEICE Trans. Electron. Kunihiko Iizuka
2009	J	`jnl`	A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS. IEEE J. Solid State Circuits Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Kunihiko Iizuka
2008	J	`jnl`	RF Variable-Gain Amplifiers and AGC Loops for Digital TV Receivers. IEICE Trans. Electron. Kunihiko Iizuka, Masato Koutani, Takeshi Mitsunaka, Hiroshi Kawamura, Shinji Toyoyama, Masayuki Miyamoto, Akira Matsuzawa
2007	J	`jnl`	A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor. IEEE J. Solid State Circuits Kunihiko Iizuka, Hiroshi Kawamura, Takanobu Fujiwara, Kanetomo Kagoshima, Shuichi Kawama, Hiroshi Kijima, Masato Koutani, Shinji Toyoyama, Keiichi Sakuno
2007	—	`conf`	A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications. ISSCC Takae Sakai, Shinya Ito, Nobuyoshi Kaiki, Atsushi Sakai, Mamoru Okazaki, Masayuki Natsumi, Akira Saito, Kazumasa Kioi, Masato Koutani, Koutani Kagoshima, Shuichi Kawama, Hiroshi Kijima, Shinji Toyoyama, Nobutoshi Matsunaga, Mutsumi Hamaguchi, Hiroshi Kawamura, Kunihiko Iizuka
2007	J	`jnl`	A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to Interferers. IEEE J. Solid State Circuits Masato Koutani, Hiroshi Kawamura, Shinji Toyoyama, Kunihiko Iizuka
2006	J	`jnl`	A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration. IEEE J. Solid State Circuits Mutsuo Daito, Hirofumi Matsui, Masaya Ueda, Kunihiko Iizuka
2006	J	`jnl`	A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s. IEEE J. Solid State Circuits Kunihiko Iizuka, Hirofumi Matsui, Masaya Ueda, Mutsuo Daito
2006	—	`conf`	Fast Automatic Tuning of Channel Selection Filters Based on Phase Delay Calibration. CICC Koutani Kagoshima, Shuichi Kawama, Shinji Toyoyama, Kunihiko Iizuka
2005	—	`conf`	A high OIP3 quadrature mixer using cross-coupled transconductor. CICC Masato Koutani, Kunihiko Iizuka
2002	J	`jnl`	Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation. IEEE J. Solid State Circuits Shin'ichiro Azuma, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz
2001	J	`jnl`	CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops. IEEE J. Solid State Circuits Kunihiko Iizuka, Masayuki Miyamoto, Yoshiji Ohta, Takahiro Suyama, Keita Hara, Shuichi Kawama, Hirofumi Matsui, Shin'ichiro Azuma, Shigenari Taguchi, Yoshihisa Fujimoto, Daniel Senderowicz
2001	—	`conf`	Embedded anti-aliasing in switched-capacitor ladder filters. CICC Daniel Senderowicz, Shin'ichiro Azuma, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto
2000	—	`conf`	A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator. CICC Yoshihisa Fujimoto, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz
1999	J	`jnl`	A parallel analog intelligent vision sensor with a variable receptive field. Syst. Comput. Jpn. Tetsuya Yagi, Seiji Kameda, Kunihiko Iizuka
1996	—	`conf`	Dynamically Adaptable CMOS Winner-Take-All Neural Network. NIPS Kunihiko Iizuka, Masayuki Miyamoto, Hirofumi Matsui