Kundan Nepal

42 papers A* 1A 6B 3C 3Misc 1Journal 14Unranked 14
YearRankTypeTitle / Venue / Authors
2025 B conf
European Test Symposium Teams: an Anniversary Snapshot.
ETS
Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2024 — conf
Dual Use Circuitry for Early Failure Warning and Test.
ISQED
Alexander Coyle, Hui Jiang, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal
2023 B conf
Harvesting Wasted Clock Cycles for Efficient Online Testing.
ETS
Eslam Yassien, Yongjia Xu, Hui Jiang, Thach Nguyen, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal
2023 J jnl
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift.
J. Electron. Test.
Hui Jiang, Fanchen Zhang, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas
2022 J jnl
Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis.
Int. J. Parallel Emergent Distributed Syst.
Dulana Rupanetti, Hassan A. Salamy, Cheol-Hong Min, Kundan Nepal
2021 J jnl
3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations.
IEEE Trans. Emerg. Top. Comput.
Soha Alhelaly, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Ping Gui, Alfred L. Crouch
2021 A conf
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits.
ITC
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar
2020 — conf
Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications.
CCWC
Dulana Rupanetti, Kundan Nepal, Hassan A. Salamy, Cheol-Hong Min
2019 — conf
Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition.
ICECS
Matthew Ward, Cheol-Hong Min, Hassan A. Salamy, Kundan Nepal
2019 — conf
Low cost Brussels sprouts harvester for small farms.
GHTC
Milad Audi, William Frost, Jose Henriquez, Nathan Jones, Janssen Hang, Kundan Nepal
2019 — conf
Low-cost instrumentation of high-tunnels for a small co-op farm.
GHTC
Jeremy Ziemer, Austin Stokes, Janssen Hang, Kundan Nepal
2019 J jnl
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack.
J. Electron. Test.
Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
2019 — conf
Test Architecture for Fine Grained Capture Power Reduction.
ICECS
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
2019 J jnl
True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors.
J. Circuits Syst. Comput.
Daniel Hellkamp, Kundan Nepal
2018 C conf
Tools for the 3Cs of Entrepreneurially Minded Learning (EML).
FIE
Heath J. LeBlanc, Kundan Nepal, Greg S. Mowry, Alan Cheville
2017 — conf
Combinational hardware Trojan detection using logic implications.
MWSCAS
Noah Cornell, Kundan Nepal
2017 — conf
Detecting a trojan die in 3D stacked integrated circuits.
NATW
Soha Alhelaly, Jennifer Dworak, Theodore W. Manikas, Ping Gui, Kundan Nepal, Alfred L. Crouch
2017 C conf
Stimulating curiosity and the ability to formulate technical questions in an electric circuits course using the question formulation technique (QFT).
FIE
Heath J. LeBlanc, Kundan Nepal, Greg S. Mowry
2016 — conf
Using Existing Reconfigurable Logic in 3D Die Stacks for Test.
NATW
Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter
2015 J jnl
Repairing a 3-D Die-Stack Using Available Programmable Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan
2013 — conf
Built-in Self-Repair in a 3D die stack using programmable logic.
DFTS
Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
2012 — conf
Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors.
NEWCAS
Kundan Nepal
2012 J jnl
Using implications to choose tests through suspect fault identification.
ACM Trans. Design Autom. Electr. Syst.
Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar
2011 B conf
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis.
ETS
Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar
2011 Misc conf
Enhancing online error detection through area-efficient multi-site implications.
VTS
Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal
2011 J jnl
Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults.
J. Comput.
Carson Dunbar, Kundan Nepal
2011 C conf
Wow! linear systems and signal processing is fun!
FIE
Maurice F. Aburdene, Kundan Nepal
2010 J jnl
A Cost Effective Approach for Online Error Detection Using Invariant Relationships.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
2010 — conf
Improving the testability and reliability of sequential circuits with invariant logic.
ACM Great Lakes Symposium on VLSI
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
2009 A conf
Compacting test vector sets via strategic use of implications.
ICCAD
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal
2009 A conf
Detecting errors using multi-cycle invariance information.
DATE
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
2008 A conf
Using Implications for Online Error Detection.
ITC
Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar
2007 J jnl
Designing Nanoscale Logic Circuits Based on Markov Random Fields.
J. Electron. Test.
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2007 A conf
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.
DATE
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2006 A conf
Designing MRF based error correcting circuits for memory elements.
DATE
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2006 J jnl
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits.
IEEE Micro
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2006 — conf
Optimizing noise-immune nanoscale circuits using principles of Markov random fields.
ACM Great Lakes Symposium on VLSI
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2006 J jnl
Timing analysis for full-custom circuits using symbolic DC formulations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein
2005 A* conf
Designing logic circuits for probabilistic computation in the presence of noise.
DAC
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2005 J jnl
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein
2004 J jnl
Design evolution of the Trinity College IGVC robot ALVIN.
J. Field Robotics
Michelle Bovard, Matthew Gillette, Trishan R. de Lanerolle, Bozidar Marinkovic, Nhon H. Trinh, Peter Votto, David J. Ahlgren, Kundan Nepal, Amir Tamrakar
2004 — conf
RESTA: a robust and extendable symbolic timing analysis tool.
ACM Great Lakes Symposium on VLSI
Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein