Kunal Korgaonkar

15 papers A* 2Misc 2Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
PustakAI: Curriculum-Aligned and Interactive Textbooks Using Large Language Models.
CoRR
Shivam Sharma, Riya Naik, Tejas Gawas, Heramb Patil, Kunal Korgaonkar
2024 — conf
Expand-Map-Reduce: A Elementary Framework for Understanding Quantum Algorithms.
HIPCW
Videet Acharya, Nakul Bhachawat, Kunal Korgaonkar
2023 Misc conf
A Data-Centric Approach for Analyzing Large-Scale Deep Learning Applications.
ICDCN
S. Sai Vineet, Natasha Meena Joseph, Kunal Korgaonkar, Arnab K. Paul
2023 Misc conf
Characteristics of Deep Learning Workloads in Industry, Academic Institutions and National Laboratories.
ICDCN
Natasha Meena Joseph, S. Sai Vineet, Kunal Korgaonkar, Arnab K. Paul
2022 J jnl
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems.
ACM J. Emerg. Technol. Comput. Syst.
Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
2021 J jnl
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems.
CoRR
Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
2021 — ed.
VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers
VLSI-SoC (Selected Papers)
Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis
2019 — —
Building Scalable Architectures Using Emerging Memory Technologies.
Kunal Korgaonkar
2019 J jnl
The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm.
CoRR
Kunal Korgaonkar, Ronny Ronen, Anupam Chattopadhyay, Shahar Kvatinsky
2019 A* conf
Vorpal: Vector Clock Ordering For Large Persistent Memory Systems.
PODC
Kunal Korgaonkar, Joseph Izraelevitz, Jishen Zhao, Steven Swanson
2018 A* conf
Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache.
ISCA
Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, Hong Wang
2015 — conf
Characterization of User's Behavior Variations for Design of Replayable Mobile Workloads.
MobiCASE
Shruti Patil, Yeseong Kim, Kunal Korgaonkar, Ibrahim Awwal, Tajana Simunic Rosing
2012 — conf
The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency.
HotPower
Ashok Gautham, Kunal Korgaonkar, Patanjali SLPSK, Shankar Balachandran, Kamakoti Veezhinathan
2011 — conf
Reconstructing Hardware Transactional Memory for Workload Optimized Systems.
APPT
Kunal Korgaonkar, Prabhat Jain, Deepak Tomar, Kashyap Garimella, Veezhinathan Kamakoti
2009 J jnl
HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions.
ACM SIGOPS Oper. Syst. Rev.
Kunal Korgaonkar, K. George, M. Gautam, V. Kamakoti