Kun-Hsien Lin

14 papers Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2024 — conf
Applications of AI in Digital Governance Services for Local Taxes- a case of the Local Tax Bureau of Taichung City Government.
DG.O
Kun-Hsien Lin, Cheng-An Shen, Su-Chuan Cheng
2022 J jnl
A Novel Beam Alignment Scheme for Mobile Millimeter-Wave Communications Based on Compressed Sensing Aided-Kalman Filter.
IEEE Open J. Commun. Soc.
Kun-Hsien Lin, Kuang-Hao Liu
2021 — conf
Using DIALux and Regression-based Machine Learning Algorithm for Designing Indoor Visible Light Positioning (VLP) and Reducing Training Data Collection.
OFC
Shao-Hua Song, Dong-Chang Lin, Yun-Han Chang, Yun-Shen Lin, Chi-Wai Chow, Yang Liu, Chien-Hung Yeh, Kun-Hsien Lin, Yi-Chang Wang, Yi-Yuan Chen
2021 — conf
Using Machine Learning and Light Spatial Sequence Arrangement for Copying Positioning Unit Cell to Reduce Training Burden in Visible Light Positioning (VLP).
WOCC
Li-Sheng Hsu, Dong-Chang Lin, Chi-Wai Chow, Tun-Yao Hung, Yun-Han Chang, Ching-Wei Peng, Yang Liu, Chien-Hung Yeh, Kun-Hsien Lin
2021 — conf
Using Pixel-per-bit Neural Network for Two Rolling Shutter Patterns Decoding in Optical Camera Communication (OCC).
WOCC
Deng-Cheng Tsai, Yun-Shen Lin, Yun-Han Chang, Li-Sheng Hsu, Chi-Wai Chow, Yang Liu, Chien-Hung Yeh, Kun-Hsien Lin
2020 — conf
Enabling Techniques for Optical Wireless Communication Systems.
OFC
Chi-Wai Chow, Chien-Hung Yeh, Yang Liu, Yinchieh Lai, Liang-Yu Wei, Chin-Wei Hsu, Guan-Hong Chen, Xin-Lan Liao, Kun-Hsien Lin
2006 J jnl
Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board.
Microelectron. Reliab.
Kun-Hsien Lin, Ming-Dou Ker
2006 J jnl
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ming-Dou Ker, Kun-Hsien Lin
2005 — conf
ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure.
ISCAS (2)
Kun-Hsien Lin, Ming-Dou Ker
2005 J jnl
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology.
IEEE J. Solid State Circuits
Ming-Dou Ker, Kun-Hsien Lin
2005 J jnl
MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process.
IEICE Trans. Electron.
Ming-Dou Ker, Kun-Hsien Lin, Che-Hao Chuang
2005 J jnl
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs.
IEEE J. Solid State Circuits
Ming-Dou Ker, Kun-Hsien Lin
2004 J jnl
Design on ESD protection scheme for IC with power-down-mode operation.
IEEE J. Solid State Circuits
Ming-Dou Ker, Kun-Hsien Lin
2004 — conf
ESD protection design for IC with power-down-mode operation.
ISCAS (2)
Ming-Dou Ker, Kun-Hsien Lin