Kun-Han Tsai - RankMe

69 papers A* 3A 17B 4C 3Misc 3Journal 15Unranked 24

Year	Rank	Type	Title / Venue / Authors
2025	Misc	`conf`	Timing-Verification Test Generation Targeting Small Delay Defects. VTS Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Kun-Han Tsai, Janusz Rajski
2021	Misc	`conf`	Timing Critical Path Validation for Intel ATOM Cores Using Structural Test. VTS Wei Li, Shih-Yu Yang, Khen Wee, Ricardo Sanchez, Jay Desai, Kun-Han Tsai, Xijiang Lin
2020	J	`jnl`	Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng
2020	J	`jnl`	GPGPU-Based ATPG System: Myth or Reality? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Liyang Lai, Kun-Han Tsai, Huawei Li
2020	A	`conf`	Test Challenges of Intel IA Cores. ITC Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, Xijiang Lin
2019	—	`conf`	Race and Glitch Handling: A Test Perspective. ITC-Asia Kun-Han Tsai
2019	—	`conf`	TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz
2018	J	`jnl`	Circuit and Methodology for Testing Small Delay Faults in the Clock Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shaofu Yang, Zhi-Yuan Wen, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2018	—	`conf`	X-Sources Analysis for Improving the Test Quality. ITC-Asia Kun-Han Tsai
2017	—	`conf`	Test Coverage Analysis for Designs with Timing Exceptions. ATS Kun-Han Tsai, Srinivasan Gopalakrishnan
2016	—	`conf`	A wide-range clock signal generation scheme for speed grading of a logic core. HPCS Shi-Yu Huang, Tzu-Heng Huang, Kun-Han Tsai, Wu-Tung Cheng
2016	J	`jnl`	Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects. IEEE Des. Test Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Tsai, Wu-Tung Cheng
2016	A	`conf`	Online slack-time binning for IO-registered die-to-die interconnects. ITC Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng
2016	B	`conf`	Testing of small delay faults in a clock network. ETS Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2016	J	`jnl`	Versatile Transition-Time Monitoring for Interconnects via Distributed TDC. IEEE Des. Test Shi-Yu Huang, Chih-Chieh Cheng, Meng-Ting Tsai, Kuan-Chen Huang, Kun-Han Tsai, Wu-Tung Cheng
2015	—	`conf`	A test-application-count based learning technique for test time reduction. VLSI-DAT Guo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng
2015	—	`conf`	Clock-domain-aware test for improving pattern compression. VLSI-DAT Kun-Han Tsai, Janusz Rajski
2015	A	`conf`	Monitoring the delay of long interconnects via distributed TDC. ITC Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2014	—	`conf`	On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs. ATS Shi-Yu Huang, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
2014	B	`conf`	On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. ETS Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
2014	J	`jnl`	Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2014	J	`jnl`	Pulse-Vanishing Test for Interposers Wires in 2.5-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
2014	—	`conf`	Testability-Driven Fault Sampling for Deterministic Test Coverage Estimation of Large Designs. ATS Kun-Han Tsai
2013	C	`conf`	At-speed BIST for interposer wires supporting on-the-spot diagnosis. IOLTS Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
2013	A	`conf`	Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. ITC Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
2013	A	`conf`	Design rule check on the clock gating logic for testability and beyond. ITC Kun-Han Tsai, Shuo Sheng
2013	—	`conf`	Improve speed path identification with suspect path expressions. VLSI-DAT Jiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo, Manish Sharma, Wu-Tung Cheng
2013	—	`conf`	Mid-bond Interposer Wire Test. Asian Test Symposium Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
2013	—	`conf`	Multicycle-aware At-speed Test Methodology. Asian Test Symposium Kun-Han Tsai, Xijiang Lin
2013	J	`jnl`	Oscillation-Based Prebond TSV Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Li-Ren Huang, Shi-Yu Huang, Stephen K. Sunter, Kun-Han Tsai, Wu-Tung Cheng
2013	J	`jnl`	Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
2013	J	`jnl`	Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
2012	A	`conf`	A unified method for parametric fault characterization of post-bond TSVs. ITC Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
2012	—	`conf`	Programmable Leakage Test and Binning for TSVs. Asian Test Symposium Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2012	A*	`conf`	Small delay testing for TSVs in 3-D ICs. DAC Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
2010	—	`conf`	A Low Complexity Transmitter Architecture and Its Application to PAPR Reduction in SFBC MIMO-OFDM Systems. ICC Chih-Peng Li, Sen-Hung Wang, Kun-Han Tsai
2010	A	`conf`	A scalable quantitative measure of IR-drop effects for scan pattern generation. ICCAD Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli
2010	—	`conf`	Improved weight assignment for logic switching activity during at-speed test pattern generation. ASP-DAC Meng-Fan Wu, Hsin-Cheih Pan, Teng-Han Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng
2010	B	`conf`	Scan based speed-path debug for a microprocessor. ETS Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz
2010	A	`conf`	Test cycle power optimization for scan-based designs. ITC Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli
2009	—	`conf`	At-Speed Scan Test Method for the Timing Optimization and Calibration. Asian Test Symposium Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng
2009	B	`conf`	Speed-Path Debug Using At-Speed Scan Test Patterns. ETS Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai
2009	J	`jnl`	Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2008	—	`conf`	A Robust Automated Scan Pattern Mismatch Debugger. ATS Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng
2008	—	`conf`	Enhancing Transition Fault Model for Delay Defect Diagnosis. ATS Wu-Tung Cheng, Brady Benware, Ruifeng Guo, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake
2008	J	`jnl`	Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2008	—	`conf`	Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2007	A	`conf`	Enhanced testing of clock faults. ITC Teresa L. McLaurin, Rich Slobodnik, Kun-Han Tsai, Ana Keim
2007	A*	`conf`	Test Generation in the Presence of Timing Exceptions and Constraints. DAC Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski
2006	J	`jnl`	Analysis and methodology for multiple-fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2006	—	`conf`	At-Speed Testing with Timing Exceptions and Constraints-Case Studies. ATS Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo
2006	—	`conf`	Delay Fault Diagnosis for Non-Robust Test. ISQED Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski
2006	Misc	`conf`	Improved Handling of False and Multicycle Paths in ATPG. VTS Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami
2006	A	`conf`	Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. ITC Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich
2006	A	`conf`	Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. ITC Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2006	—	`conf`	Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo
2005	A	`conf`	Built-in constraint resolution. ITC Grady Giles, Joel Irby, Daniela Toneva, Kun-Han Tsai
2005	J	`jnl`	Delay-fault diagnosis using timing information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2004	—	`conf`	Compactor Independent Direct Diagnosis. Asian Test Symposium Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski
2004	—	`conf`	Delay Fault Diagnosis Using Timing Information. ISQED Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2004	C	`conf`	Diagnosis of Hold Time Defects. ICCD Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2004	A	`conf`	Realizing High Test Quality Goals with Smart Test Resource Usage. ITC Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski
2003	A	`conf`	An Efficient and Effective Methodology on the Multiple Fault Diagnosis. ITC Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
2003	A	`conf`	Impact of Multiple-Detect Test Patterns on Product Quality. ITC Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski
2003	C	`conf`	Multiple Fault Diagnosis Using n-Detection Tests. ICCD Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2002	A	`conf`	Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
2000	J	`jnl`	Star test: the theory and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska
1997	A*	`conf`	STARBIST: Scan Autocorrelated Random Pattern Generation. DAC Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska
1997	A	`conf`	Scan-Encoded Test Pattern Generation for BIST. ITC Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski