Kumiko Nomura

22 papers A 1B 1C 7Misc 1Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2024 J jnl
Synchronized Stepwise Control of Firing and Learning Thresholds in a Spiking Randomly Connected Neural Network toward Hardware Implementation.
CoRR
Kumiko Nomura, Yoshifumi Nishi
2020 C conf
Dynamic Firing on Static Analog/Digital Neuron Circuits with Resistive Synapses for Time-Series Neural Network.
ISCAS
Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Kumiko Nomura, Koichi Mizushima, Yoshifumi Nishi
2019 C conf
Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning.
ISCAS
Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Radu Berdan, Kumiko Nomura, Yoshifumi Nishi
2018 C conf
Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays.
ISCAS
Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi
2017 — conf
Novel memory hierarchy with e-STT-MRAM for near-future applications.
VLSI-DAT
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
2014 — conf
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.
ISIC
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
2014 — conf
Novel nonvolatile memory hierarchies to realize "normally-off mobile processors".
ASP-DAC
Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe
2013 A conf
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.
DATE
Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
2012 — conf
Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation.
IPDPS Workshops
Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita
2010 C conf
Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies.
ISCAS
Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima
2009 J jnl
On the two-dimensional orthogonal drawing of series-parallel graphs.
Discret. Appl. Math.
Satoshi Tayu, Kumiko Nomura, Shuichi Ueno
2009 C conf
Perspectives and Issues in 3D-IC from Designers' Point of View.
ISCAS
Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto
2008 C conf
On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract).
ISCAS
Satoshi Tayu, Kumiko Nomura, Shuichi Ueno
2007 J jnl
3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
2006 — conf
3D on-chip networking technology based on post-silicon devices for future networks-on-chip.
Nano-Net
Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
2006 — conf
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices.
Nano-Net
Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon
2006 C conf
On the two-dimensional orthogonal drawing of series-parallel graphs.
ISCAS
Satoshi Tayu, Kumiko Nomura, Shuichi Ueno
2005 J jnl
On the Orthogonal Drawing of Outerplanar Graphs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kumiko Nomura, Satoshi Tayu, Shuichi Ueno
2004 Misc conf
On the Orthogonal Drawing of Outerplanar Graphs.
COCOON
Kumiko Nomura, Satoshi Tayu, Shuichi Ueno
2004 J jnl
Sparse networks tolerating random faults.
Discret. Appl. Math.
Toshinori Yamada, Kumiko Nomura, Shuichi Ueno
2003 — conf
Optimal adaptive parallel diagnosis for arrays.
ISCAS (3)
Toshinori Yamada, Kumiko Nomura, Shuichi Ueno
2001 B conf
On Adaptive Fault Diagnosis for Multiprocessor Systems.
ISAAC
Kumiko Nomura, Toshinori Yamada, Shuichi Ueno