Kumar Y. B. Nithin

22 papers C 5Misc 4Journal 1Unranked 12

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	An Error Bound Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Kumar Y. B. Nithin
2021	Misc	`conf`	A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. VLSID Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini
2020	—	`conf`	A 1.8 V, Mode-Configurable Hybrid Smart ADC. iSES Tejas J. Shahane, Siddharth R. K., Kumar Y. B. Nithin, Vasantha M. H.
2018	C	`conf`	A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications. ISCAS Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha, Edoardo Bonizzoni
2018	Misc	`conf`	A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range. VLSID P. S. Veerendranath, M. H. Vasantha, Kumar Y. B. Nithin, Edoardo Bonizzoni
2018	—	`conf`	Design of Approximate Dividers for Error Tolerant Applications. MWSCAS Karri Manikantta Reddy, M. H. Vasantha, Kumar Y. B. Nithin, Devesh Dwivedi
2018	—	`conf`	Performance Enhancement of Split Length Compensated Operational Amplifiers. ISVLSI Donel Anto, Abhijeet D. Taralkar, Kumar Y. B. Nithin, M. H. Vasantha
2017	—	`conf`	A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection. ISVLSI Rakhi R., Abhijeet D. Taralkar, M. H. Vasantha, Kumar Y. B. Nithin
2017	—	`conf`	Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. ISVLSI Sumit Khalapure, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
2017	—	`conf`	Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. ISVLSI S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
2016	—	`conf`	A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core. ISVLSI B. Naresh Kumar Reddy, M. H. Vasantha, Kumar Y. B. Nithin
2016	Misc	`conf`	Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. VLSID A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha
2016	—	`conf`	Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor. ISVLSI S. Ahish, Dheeraj Sharma, M. H. Vasantha, Kumar Y. B. Nithin
2016	—	`conf`	Design of Low Power 5-Bit Hybrid Flash ADC. ISVLSI S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
2016	—	`conf`	FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. ICCCNT Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha
2015	—	`conf`	Low power, high speed error tolerant multiplier using approximate adders. VDAT Karri Manikantta Reddy, Kumar Y. B. Nithin, Dheeraj Sharma, M. H. Vasantha
2013	C	`conf`	A 1.96-mW, 2.6-MHz bandwidth discrete time quadrature band-pass ΣΔ modulator. ISCAS Kumar Y. B. Nithin, Hervé Caracciolo, Edoardo Bonizzoni, A. Parra, Franco Maloberti
2013	Misc	`conf`	Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators. VLSI Design Kumar Y. B. Nithin, Edoardo Bonizzoni, Amit Patra, Franco Maloberti
2012	C	`conf`	Interference rejection in delay line based quadrature band-pass ΣΔ modulators. ISCAS Kumar Y. B. Nithin, Edoardo Bonizzoni, Amit Patra, Franco Maloberti
2009	C	`conf`	Complex Cascaded Bandpass SigmaDelta ADC Design. ISCAS Kumar Y. B. Nithin, Selçuk Talay, Franco Maloberti
2009	C	`conf`	Slew-rate and Gain Enhancement in Two Stage Operational Amplifiers. ISCAS Aldo Pena-Perez, Kumar Y. B. Nithin, Edoardo Bonizzoni, Franco Maloberti
2008	—	`conf`	On the design of band-pass quadrature ΣΔ modulators. APCCAS Kumar Y. B. Nithin, Selçuk Talay, Franco Maloberti