Kuen-Jong Lee

133 papers A* 1A 21B 2C 5Misc 7Journal 44Unranked 53
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Universal Sequential Authentication Scheme for TAPC-Based Test Standards.
IEEE Trans. Very Large Scale Integr. Syst.
Guan-Rong Chen, Kuen-Jong Lee
2025 A conf
Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion.
ITC
Cheng-En Chung, Jun-Han Jian, Kuen-Jong Lee, Nan-Hsin Tseng, Hsin-Wei Hung, Hao-Yu Yang, Dong-Yi Chen
2024 — conf
A Lightweight Memory Protection Scheme with Criticality-Aware Encryption and Embedded MAC for Secure DNN Accelerators.
APCCAS
Yu-Chuan Lin, Kuen-Jong Lee
2024 — conf
An On-chip High-resolution Delay Measurement Scheme for TSVs in 3DIC.
APCCAS
Dong-Yi Chen, Cheng-Hong Lee, Kuen-Jong Lee, Nan-Hsin Tseng, Hsin-Wei Hung, Hao-Yu Yang
2022 J jnl
A Dynamic-Key Based Secure Scan Architecture for Manufacturing and In-Field IC Testing.
IEEE Trans. Emerg. Top. Comput.
Kuen-Jong Lee, Ching-An Liu, Chia-Chi Wu
2022 J jnl
A Secure JTAG Wrapper for SoC Testing and Debugging.
IEEE Access
Kuen-Jong Lee, Zheng-Yao Lu, Shih-Chun Yeh
2022 Misc conf
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations.
VTS
Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
2022 — conf
An Authentication-Based Secure IJTAG Network.
ATS
Shih-Chun Yeh, Kuen-Jong Lee, Dong-Yi Chen
2022 J jnl
An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuen-Jong Lee, Cheng-Hung Wu, Tsung-Yu Hou
2022 — conf
Diagnosing Transition Delay Faults under Scan-Based Logic Array.
ITC-Asia
Duo-Yao Kang, Shiou-Ning Lin, Kuen-Jong Lee
2022 J jnl
Efficient Test Compression Configuration Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski
2022 A conf
Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks.
ITC
Yan-Fu Chen, Duo-Yao Kang, Kuen-Jong Lee
2022 J jnl
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function.
J. Electron. Test.
Zhi-Wei Lai, Po-Hua Huang, Kuen-Jong Lee
2021 — conf
Lightweight Hardware-Based Memory Protection Mechanism on IoT Processors.
ATS
Hung-Yao Chi, Kuen-Jong Lee, Tzu-Chun Jao
2021 J jnl
Test Chips With Scan-Based Logic Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu-Hsiang Chen, Chia-Ming Hsu, Kuen-Jong Lee
2020 B conf
Efficient Prognostication of Pattern Count with Different Input Compression Ratios.
ETS
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
2020 — conf
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels.
ITC-Asia
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
2020 J jnl
Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy
2020 A conf
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.
ITC
Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
2019 — conf
A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model.
VLSI-DAT
Chao-Jun Shang, Cheng-Hung Wu, Kuen-Jong Lee, Yu-Hsiang Chen
2019 J jnl
An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction.
IEEE Trans. Very Large Scale Integr. Syst.
Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy
2019 — conf
Deep Learning Based Test Compression Analyzer.
ATS
Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye
2019 A conf
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia.
ITC
Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian
2019 J jnl
On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuen-Jong Lee, Bo-Ren Chen, Michael Andreas Kochte
2019 — conf
Time-Related Hardware Trojan Attacks on Processor Cores.
ITC-Asia
Man-Hsuan Kuo, Chun-Ming Hu, Kuen-Jong Lee
2019 — conf
Using Unstable SRAM Bits for Physical Unclonable Function Applications on Off-The-Shelf SRAM.
APCCAS
Zhi-Wei Lai, Kuen-Jong Lee
2018 — conf
A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks.
ATS
Chia-Chi Wu, Man-Hsuan Kuo, Kuen-Jong Lee
2018 J jnl
A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip.
IEEE Trans. Computers
Chun-Wei Wu, Kuen-Jong Lee, Alan P. Su
2018 J jnl
A Repair-for-Diagnosis Methodology for Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Cheng-Hung Wu, Sheng-Lin Lin, Kuen-Jong Lee, Sudhakar M. Reddy
2018 A conf
Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run.
ITC
Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy
2018 — conf
Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run.
ITC-Asia
Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy
2017 — conf
A low power synthesis flow for multi-rate systems.
VLSI-DAT
Hsin-Pang Kuo, Alan P. Su, Kuen-Jong Lee
2017 — conf
A run-pause-resume silicon debug technique for multiple clock domain systems.
ITC-Asia
Shuo-Lian Hong, Kuen-Jong Lee
2017 A conf
A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems.
ITC
Shuo-Lian Hong, Kuen-Jong Lee
2017 J jnl
Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wen-Hsuan Hsu, Michael Andreas Kochte, Kuen-Jong Lee
2017 — conf
Test Compression with Single-Input Data Spreader and Multiple Test Sessions.
ATS
Chang-Wen Chen, Yi-Cheng Kong, Kuen-Jong Lee
2017 J jnl
Test Stimulus Compression Based on Broadcast Scan With One Single Input.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jhen-Zong Chen, Kuen-Jong Lee
2017 — conf
Test generation for open and delay faults in CMOS circuits.
ITC-Asia
Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy
2016 — conf
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling.
ASP-DAC
Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin
2016 A conf
An on-chip self-test architecture with test patterns recorded in scan chains.
ITC
Kuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte
2016 — conf
Autonomous Testing for 3D-ICs with IEEE Std. 1687.
ATS
Jin-Cun Ye, Michael A. Kochte, Kuen-Jong Lee, Hans-Joachim Wunderlich
2016 A conf
Output bit selection methodology for test response compaction.
ITC
Wei-Cheng Lien, Kuen-Jong Lee
2016 — conf
Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis.
ATS
Sheng-Lin Lin, Cheng-Hung Wu, Kuen-Jong Lee
2016 — conf
Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults.
ASP-DAC
Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee
2016 A conf
Transformation of multiple fault models to a unified model for ATPG efficiency enhancement.
ITC
Cheng-Hung Wu, Kuen-Jong Lee
2015 A conf
A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC.
DATE
Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee
2015 — conf
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST.
ASP-DAC
Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu
2015 — conf
Distinguishing dynamic bridging faults and transition delay faults.
ASICON
Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee
2015 — conf
Improve transition fault diagnosability via observation point insertion.
VLSI-DAT
Cheng-Hung Wu, Yi-da Wang, Kuen-Jong Lee
2014 — conf
An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults.
ATS
Cheng-Hung Wu, Kuen-Jong Lee
2014 Misc conf
An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model.
VTS
Cheng-Hung Wu, Kuen-Jong Lee, Wei-Cheng Lien
2014 A conf
An efficient diagnosis-aware pattern generation procedure for transition faults.
ITC
Kuen-Jong Lee, Cheng-Hung Wu
2014 J jnl
Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, Kuen-Jong Lee
2014 J jnl
Efficient LFSR Reseeding Based on Internal-Response Feedback.
J. Electron. Test.
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty
2014 J jnl
On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions.
IEEE Trans. Very Large Scale Integr. Syst.
Chin-Yao Chang, Kuen-Jong Lee
2014 — conf
Output selection for test response compaction based on multiple counters.
VLSI-DAT
Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh
2014 B conf
Output-bit selection with X-avoidance using multiple counters for test-response compaction.
ETS
Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh
2013 — conf
A New LFSR Reseeding Scheme via Internal Response Feedback.
Asian Test Symposium
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty
2013 J jnl
An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Wee-Lung Ang
2013 — conf
An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip.
VLSI-DAT
Kuen-Jong Lee, Chin-Yao Chang, Hung-Yang Yang
2013 J jnl
Counter-Based Output Selection for Test Response Compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty, Yu-Hua Wu
2012 — conf
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume.
Asian Test Symposium
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh
2012 C conf
Accumulator-based output selection for test response compaction.
ISCAS
Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Shih-Shiun Chien, Krishnendu Chakrabarty
2012 J jnl
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
2012 — conf
Routing-efficient implementation of an internal-response-based BIST architecture.
VLSI-DAT
Wei-Cheng Lien, Tong-Yu Hsieh, Kuen-Jong Lee
2011 — conf
A software/hardware co-debug platform for multi-core systems.
ASICON
Kuen-Jong Lee, Alan P. Su, Long-Feng Chen, Jia-Wei Jhou, Jiff Kuo, Mark Liu
2011 J jnl
An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2011 Misc conf
EPIDETOX: an ESL platform for integrated circuit design and tool exploration.
CODES+ISSS
Kuen-Jong Lee, Chin-Yao Chang, I-Jou Chen
2011 J jnl
Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores.
IEEE Trans. Very Large Scale Integr. Syst.
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
2011 J jnl
Programmable System-on-Chip for Silicon Prototyping.
IEEE Trans. Ind. Electron.
Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chi-Shi Chen, Jiann-Jenn Wang, Kuen-Jong Lee, Chin-Long Wey
2011 J jnl
Test Response Compaction via Output Bit Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuen-Jong Lee, Wei-Cheng Lien, Tong-Yu Hsieh
2010 — conf
A Complete Logic BIST Technology with No Storage Requirement.
Asian Test Symposium
Wei-Cheng Lien, Kuen-Jong Lee
2010 J jnl
On-Chip SOC Test Platform Design Based on IEEE 1500 Standard.
IEEE Trans. Very Large Scale Integr. Syst.
Kuen-Jong Lee, Tong-Yu Hsieh, Chin-Yao Chang, Yu-Ting Hong, Wen-Cheng Huang
2009 — conf
A low-cost SOC debug platform based on on-chip test architectures.
SoCC
Kuen-Jong Lee, Si-Yuan Liang, Alan P. Su
2009 C conf
Full System Simulation and Verification Framework.
IAS
Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao
2009 A conf
Tolerance of performance degrading faults for effective yield improvement.
ITC
Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee
2009 — conf
Transaction Level Modeling and Design Space Exploration for SOC Test Architectures.
Asian Test Symposium
Chin-Yao Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, Alan P. Su
2009 J jnl
Turbo1500: Core-Based Design for Test and Diagnosis.
IEEE Des. Test Comput.
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
2008 — conf
A Software-Based Test Methodology for Direct-Mapped Data Cache.
ATS
Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen
2008 C conf
A hybrid self-testing methodology of processor cores.
ISCAS
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
2008 Misc conf
A hybrid software-based self-testing methodology for embedded processor.
SAC
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
2008 J jnl
An Error Rate Based Test Methodology to Support Error-Tolerance.
IEEE Trans. Reliab.
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2008 A conf
Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.
ITC
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
2007 A conf
Reduction of detected acceptable faults for yield improvement via error-tolerance.
DATE
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2007 — conf
Test Efficiency Analysis and Improvement of SOC Test Platforms.
ATS
Tong-Yu Hsieh, Kuen-Jong Lee, Jian-Jhih You
2006 Misc conf
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance.
VTS
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2006 — conf
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.
SoCC
Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou
2005 — conf
A complete memory address generator for scan based March algorithms.
MTDT
Wei-Lun Wang, Kuen-Jong Lee
2005 — conf
A high speed BIST architecture for DDR-SDRAM testing.
MTDT
Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee
2005 A conf
A novel test methodology based on error-rate to support error-tolerance.
ITC
Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
2005 — conf
An embedded processor based SOC test platform.
ISCAS (3)
Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong
2004 — conf
A Low-Cost Diagnosis Methodology for Pipelined A/D Converters.
Asian Test Symposium
Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang
2004 — conf
Test Power Reduction with Multiple Capture Orders.
Asian Test Symposium
Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho
2003 — conf
A Sigma-Delta Modulation Based BIST Scheme for A/D Converters.
Asian Test Symposium
Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng
2003 J jnl
Test pattern generation and clock disabling for simultaneous test time and power reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee
2002 J jnl
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment.
J. Electron. Test.
Wei-Lun Wang, Kuen-Jong Lee
2002 J jnl
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.
J. Electron. Test.
Kuen-Jong Lee, Tsung-Chu Huang
2002 J jnl
An efficient BIST method for distributed small buffers.
IEEE Trans. Very Large Scale Integr. Syst.
Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee
2002 J jnl
Guest Editorial.
J. Electron. Test.
Kuen-Jong Lee, Chau-Chin Su
2002 — conf
Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling.
Asian Test Symposium
Kuen-Jong Lee, Jih-Jeen Chen
2001 — conf
A Low-Power LFSR Architecture.
Asian Test Symposium
Tsung-Chu Huang, Kuen-Jong Lee
2001 A conf
A token scan architecture for low power testing.
ITC
Tsung-Chu Huang, Kuen-Jong Lee
2001 J jnl
An on-chip march pattern generator for testing embedded memory cores.
IEEE Trans. Very Large Scale Integr. Syst.
Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang
2001 J jnl
Analysis and generation of control and observation structures foranalog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yun-Che Wen, Kuen-Jong Lee
2001 J jnl
Reduction of power consumption in scan-based circuits during testapplication by an input control technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsung-Chu Huang, Kuen-Jong Lee
2000 — conf
A hierarchical test control architecture for core based design.
Asian Test Symposium
Kuen-Jong Lee, Cheng-I Huang
2000 — conf
Accelerated test pattern generators for mixed-mode BIST environments.
Asian Test Symposium
Wei-Lun Wang, Kuen-Jong Lee
2000 A conf
An on Chip ADC Test Structure.
DATE
Yun-Che Wen, Kuen-Jong Lee
2000 — conf
Peak-power reduction for multiple-scan circuits during test application.
Asian Test Symposium
Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen
1999 Misc conf
An Efficient BIST Method for Small Buffers.
VTS
Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee
1999 — conf
An Input Control Technique for Power Reduction in Scan Circuits During Test Application.
Asian Test Symposium
Tsung-Chu Huang, Kuen-Jong Lee
1999 J jnl
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.
ACM Trans. Design Autom. Electr. Syst.
Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang
1999 J jnl
Broadcasting test patterns to multiple circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang
1998 J jnl
A General Structure of Feedback Shift Registers for Built-In Self Test.
J. Inf. Sci. Eng.
Kuen-Jong Lee, Wei-Lun Wang, Jhing-Fa Wang
1998 J jnl
A graph representation for programmable logic arrays to facilitate testing and logic design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu
1998 J jnl
Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters.
J. Inf. Sci. Eng.
Kuen-Jong Lee, Cheng-Hsuing Kuo
1998 — conf
On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation.
Asian Test Symposium
Kuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh
1998 A conf
Using a single input to support multiple scan chains.
ICCAD
Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang
1997 — conf
Built-in current sensor designs based on the bulk-driven technique.
Asian Test Symposium
Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee
1996 — conf
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.
Asian Test Symposium
Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai
1996 — conf
Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.
Asian Test Symposium
Kuen-Jong Lee, Jing-Jou Tang
1995 C conf
A New Architecture for Analog Boundary Scan.
ISCAS
Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee
1995 J jnl
A practical current sensing technique for I
IEEE Trans. Very Large Scale Integr. Syst.
Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu
1995 C conf
An I
ISCAS
Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee
1995 J jnl
An integrated system for assigning signal flow directions to CMOS transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer
1995 — conf
Built-in intermediate voltage testing for CMOS circuits.
ED&TC
Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu
1994 J jnl
SWiTEST: a switch level test generation system for CMOS combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
1992 A conf
A Fast Testing Method for Sequential Circuits at the State Trasition Level.
ITC
Wei-Lun Wang, Jhing-Fa Wang, Kuen-Jong Lee
1992 J jnl
Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuen-Jong Lee, Melvin A. Breuer
1992 A* conf
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits.
DAC
Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
1991 Misc conf
Constraints for using IDDQ testing to detect CMOS bridging faults.
VTS
Kuen-Jong Lee, Melvin A. Breuer
1990 A conf
A New Method for Assigning Signal Flow Directions to MOS Transistors.
ICCAD
Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer
1990 A conf
On the charge sharing problem in CMOS stuck-open fault testing.
ITC
Kuen-Jong Lee, Melvin A. Breuer