Kuen-Di Lee

14 papers C 3Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2017 J jnl
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang, Wei Hwang, Ming-Hsien Tu, Sheng-Chi Lung, Wei-Sheng Peng, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang
2016 J jnl
A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line.
Microelectron. J.
Shang-Lin Wu, Chien-Yu Lu, Ming-Hsien Tu, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang
2015 J jnl
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist.
IEEE Trans. Very Large Scale Integr. Syst.
Chien-Yu Lu, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Ya-Ping Wu, Chung-Ping Huang, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
2014 — conf
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists.
SoCC
Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
2013 C conf
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist.
ISCAS
Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih
2012 J jnl
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist.
IEEE Trans. Circuits Syst. II Express Briefs
Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
2012 — conf
A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist.
SoCC
Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2012 J jnl
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing.
IEEE J. Solid State Circuits
Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang Shih, Shyh-Jye Jou, Ching-Te Chuang
2012 — conf
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array.
VLSI-DAT
Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih
2012 C conf
An all-digital bit transistor characterization scheme for CMOS 6T SRAM array.
ISCAS
Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
2012 — conf
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM.
APCCAS
Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
2012 — conf
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array.
VLSI-DAT
Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang
2012 C conf
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder.
ISCAS
Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2011 — conf
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
SoCC
Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu