Kubilay Atasu - RankMe

56 papers A* 7A 2B 6Misc 3Journal 27Unranked 10

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Graph Feature Preprocessor: Real-time Extraction of Subgraph-based Features from Transaction Graphs. CoRR Jovan Blanusa, Maximo Cravero Baraja, Andreea Anghel, Luc von Niederhäusern, Erik R. Altman, Haris Pozidis, Kubilay Atasu
2024	—	`conf`	Graph Feature Preprocessor: Real-time Subgraph-based Feature Extraction for Financial Crime Detection. ICAIF Jovan Blanusa, Maximo Cravero Baraja, Andreea Anghel, Luc von Niederhäusern, Erik R. Altman, Haris Pozidis, Kubilay Atasu
2024	J	`jnl`	Multigraph Message Passing with Bi-Directional Multi-Edge Aggregations. CoRR H. Çagri Bilgi, Lydia Y. Chen, Kubilay Atasu
2024	A*	`conf`	Provably Powerful Graph Neural Networks for Directed Multigraphs. AAAI Béni Egressy, Luc von Niederhäusern, Jovan Blanusa, Erik R. Altman, Roger Wattenhofer, Kubilay Atasu
2023	J	`jnl`	Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles. CoRR Jovan Blanusa, Kubilay Atasu, Paolo Ienne
2023	J	`jnl`	Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles. ACM Trans. Parallel Comput. Jovan Blanusa, Kubilay Atasu, Paolo Ienne
2023	J	`jnl`	Provably Powerful Graph Neural Networks for Directed Multigraphs. CoRR Béni Egressy, Luc von Niederhäusern, Jovan Blanusa, Erik R. Altman, Roger Wattenhofer, Kubilay Atasu
2023	A*	`conf`	Realistic Synthetic Financial Transactions for Anti-Money Laundering Models. NeurIPS Erik R. Altman, Jovan Blanusa, Luc von Niederhäusern, Beni Egressy, Andreea Anghel, Kubilay Atasu
2023	J	`jnl`	Realistic Synthetic Financial Transactions for Anti-Money Laundering Models. CoRR Erik R. Altman, Béni Egressy, Jovan Blanusa, Kubilay Atasu
2022	B	`conf`	Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. SPAA Jovan Blanusa, Paolo Ienne, Kubilay Atasu
2022	J	`jnl`	Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. CoRR Jovan Blanusa, Paolo Ienne, Kubilay Atasu
2020	J	`jnl`	Many-Core Clique Enumeration with Fast Set Intersections. Proc. VLDB Endow. Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu
2020	—	`conf`	Parallelizing Maximal Clique Enumeration on Modern Manycore Processors. IPDPS Workshops Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu
2020	J	`jnl`	Tera-scale coordinate descent on GPUs. Future Gener. Comput. Syst. Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis
2019	J	`jnl`	Addressing Interpretability and Cold-Start in Matrix Factorization for Recommender Systems. IEEE Trans. Knowl. Data Eng. Michail Vlachos, Celestine Dünner, Reinhard Heckel, Vassilios G. Vassiliadis, Thomas P. Parnell, Kubilay Atasu
2019	A*	`conf`	Linear-Complexity Data-Parallel Earth Mover's Distance Approximations. ICML Kubilay Atasu, Thomas Mittelholzer
2018	J	`jnl`	A hardware compilation framework for text analytics queries. J. Parallel Distributed Comput. Raphael Polig, Kubilay Atasu, Heiner Giefers, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee
2018	J	`jnl`	Faster Text Similarity Using a Linear-Complexity Relaxed Word Mover's Distance. ERCIM News Kubilay Atasu, Vasileios Vasileiadis, Michail Vlachos
2018	J	`jnl`	Giving Text Analytics a Boost. CoRR Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Eva Sitaridi, Huaiyu Zhu
2018	J	`jnl`	Low-Complexity Data-Parallel Earth Mover's Distance Approximations. CoRR Kubilay Atasu, Thomas Mittelholzer
2017	J	`jnl`	Foreword to the Special Section on Reconfigurable Computing. J. Signal Process. Syst. Steven Derrien, Kubilay Atasu, João M. P. Cardoso, Jürgen Becker
2017	B	`conf`	High-Performance Recommender System Training Using Co-Clustering on CPU/GPU Clusters. ICPP Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Michail Vlachos, Haralampos Pozidis
2017	—	`conf`	Large-Scale Stochastic Learning Using GPUs. IPDPS Workshops Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haris Pozidis
2017	J	`jnl`	Large-Scale Stochastic Learning using GPUs. CoRR Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haris Pozidis
2017	J	`jnl`	Linear-Complexity Relaxed Word Mover's Distance with GPU Acceleration. CoRR Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Manolis Sifalakis, Haralampos Pozidis, Vasileios Vasileiadis, Michail Vlachos, Cesar Berrospi, Abdel Labbi
2017	—	`conf`	Linear-complexity relaxed word Mover's distance with GPU acceleration. IEEE BigData Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Manolis Sifalakis, Haralampos Pozidis, Vasileios Vasileiadis, Michail Vlachos, Cesar Berrospi, Abdel Labbi
2017	—	`conf`	Understanding and optimizing the performance of distributed machine learning applications on apache spark. IEEE BigData Celestine Dünner, Thomas P. Parnell, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis
2016	B	`conf`	Annotation-based finite-state transducers on reconfigurable devices. FPL Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama
2016	J	`jnl`	Feature-rich Regular Expression Matching Accelerator for Text Analytics. J. Signal Process. Syst. Kubilay Atasu
2016	J	`jnl`	High-Performance Distributed Machine Learning using Apache SPARK. CoRR Celestine Dünner, Thomas P. Parnell, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis
2015	—	`conf`	Leftmost longest regular expression matching in reconfigurable logic. FPT Kubilay Atasu
2014	B	`conf`	Compiling text analytics queries to FPGAs. FPL Raphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu
2014	J	`jnl`	Giving Text Analytics a Boost. IEEE Micro Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Huaiyu Zhu, Eva Sitaridi
2014	J	`jnl`	Guest Editorial: Application Specific Processors and Architectures. J. Signal Process. Syst. Melissa C. Smith, Kubilay Atasu
2014	—	`conf`	Hardware-accelerated text analytics. Hot Chips Symposium Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee
2014	—	`conf`	Resource-efficient regular expression matching architecture for text analytics. ASAP Kubilay Atasu
2013	J	`jnl`	Exploring the design space of programmable regular expression matching accelerators. J. Syst. Archit. Kubilay Atasu, Raphael Polig, Jonathan Rohrer, Christoph Hagleitner
2013	A	`conf`	Hardware-Accelerated Regular Expression Matching with Overlap Handling on IBM PowerEN Processor. IPDPS Kubilay Atasu, Florian Dörfler, Jan van Lunteren, Christoph Hagleitner
2013	B	`conf`	Hardware-accelerated regular expression matching for high-throughput text analytics. FPL Kubilay Atasu, Raphael Polig, Christoph Hagleitner, Frederick R. Reiss
2013	B	`conf`	Token-based dictionary pattern matching for text analytics. FPL Raphael Polig, Kubilay Atasu, Christoph Hagleitner
2012	J	`jnl`	Complexity of Computing Convex Subgraphs in Custom Instruction Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Joseph Reddington, Kubilay Atasu
2012	A*	`conf`	Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator. MICRO Jan van Lunteren, Christoph Hagleitner, Timothy Heil, Giora Biran, Uzi Shvadron, Kubilay Atasu
2012	J	`jnl`	FISH: Fast Instruction SyntHesis for Custom Processors. IEEE Trans. Very Large Scale Integr. Syst. Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar
2012	A*	`conf`	Proving correctness of regular expression accelerators. DAC Mitra Purandare, Kubilay Atasu, Christoph Hagleitner
2009	Misc	`conf`	Memory-efficient distribution of regular expressions for fast deep packet inspection. CODES+ISSS Jonathan Rohrer, Kubilay Atasu, Jan van Lunteren, Christoph Hagleitner
2008	J	`jnl`	CHIPS: Custom Hardware Instruction Processor Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk
2008	—	`conf`	Fast custom instruction identification by convex subgraph enumeration. ASAP Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar
2007	—	`—`	Hardware/software partitioning for custom instruction processors (Özelleştirilebilir komut kümeli işlemciler için yazılım/donanım bölüştürmesi) Kubilay Atasu
2007	A	`conf`	Optimizing instruction-set extensible processors under data bandwidth constraints. DATE Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar
2006	J	`jnl`	Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Laura Pozzi, Kubilay Atasu, Paolo Ienne
2006	—	`conf`	Towards optimal custom instruction processors. Hot Chips Symposium Wayne Luk, Kubilay Atasu, Robert G. Dimond, Oskar Mencer
2005	Misc	`conf`	An integer linear programming approach for identifying instruction-set extensions. CODES+ISSS Kubilay Atasu, Günhan Dündar, Can C. Özturan
2004	Misc	`conf`	Efficient AES implementations for ARM based platforms. SAC Kubilay Atasu, Luca Breveglieri, Marco Macchetti
2004	A*	`conf`	Introduction of local memory elements in instruction set extensions. DAC Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt
2003	J	`jnl`	Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. Int. J. Parallel Program. Kubilay Atasu, Laura Pozzi, Paolo Ienne
2003	A*	`conf`	Automatic application-specific instruction-set extensions under microarchitectural constraints. DAC Kubilay Atasu, Laura Pozzi, Paolo Ienne