Kuang-Chien Chen

37 papers A* 7A 10C 2Misc 1Journal 8Unranked 8

Year	Rank	Type	Title / Venue / Authors
2005	A	`conf`	An Efficient Sequential SAT Solver With Improved Search Strategies. DATE Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen
2004	J	`jnl`	A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. IEEE Des. Test Comput. Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen
2002	—	`conf`	A Practical Approach to Cycle Bound Estimation for Property Checking. IWLS Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou
2001	J	`jnl`	Verifying sequential equivalence using ATPG techniques. ACM Trans. Design Autom. Electr. Syst. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
2000	J	`jnl`	AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer
1999	J	`jnl`	AutoFix: a hybrid tool for automatic logic rectification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
1999	J	`jnl`	Logic synthesis for engineering change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska
1998	J	`jnl`	Cost-free scan: a low-overhead scan path design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen
1998	A*	`conf`	Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu
1997	—	`conf`	AQUILA: An equivalence verifier for large sequential circuits. ASP-DAC Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
1997	A	`conf`	Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. ITC Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng
1997	Misc	`conf`	Incremental logic rectification. VTS Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
1996	A	`conf`	A novel methodology for transistor-level power estimation. ISLPED Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee
1996	A	`conf`	An ATPG-Based Framework for Verifying Sequential Equivalence. ITC Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser
1996	A*	`conf`	Compact Vector Generation for Accurate Power Simulation. DAC Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee
1996	A*	`conf`	Error Correction Based on Verification Techniques. DAC Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
1996	—	`conf`	On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
1996	—	`conf`	Sequential Permissible Functions and their Application to Circuit Optimization. ED&TC Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee
1995	A	`conf`	Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. FPGA Anmol Mathur, Kuang-Chien Chen, C. L. Liu
1995	A	`conf`	Cost-free scan: a low-overhead scan path design methodology. ICCAD Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen
1995	A*	`conf`	Logic Synthesis for Engineering Change. DAC Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
1995	—	`conf`	Logic rectification and synthesis for engineering change. ASP-DAC Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen
1995	A	`conf`	Re-engineering of timing constrained placements for regular architectures. ICCAD Anmol Mathur, Kuang-Chien Chen, C. L. Liu
1994	J	`jnl`	LUT-based FPGA technology mapping under arbitrary net-delay models. Comput. Graph. Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen
1993	—	`conf`	A performance driven hierarchical partitioning placement algorithm. EURO-DAC Tong Gao, Chung Laung (Dave) Liu, Kuang-Chien Chen
1993	—	`conf`	Boolean matching based on Boolean unification. EURO-DAC Kuang-Chien Chen
1992	C	`conf`	An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen
1992	J	`jnl`	DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Des. Test Comput. Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar
1992	A*	`conf`	Efficient Sum-to-One Subsets Algorithm for Logic Optimization. DAC Kuang-Chien Chen, Masahiro Fujita
1992	—	`conf`	Maximal reduction of lookup-table based FPGAs. EURO-DAC Kuang-Chien Chen, Jason Cong
1991	A*	`conf`	A Resynthesis Approach for Network Optimization. DAC Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
1991	A	`conf`	Application of Boolean Unification to Combinational Logic Synthesis. ICCAD Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen
1991	C	`conf`	Concurrent Resynthesis for Network Optimization. ICCD Kuang-Chien Chen, Masahiro Fujita
1991	—	`—`	Logic synthesis and optimization algorithms Kuang-Chien Chen
1990	A*	`conf`	Timing Optimization for Multi-Level Combinational Networks. DAC Kuang-Chien Chen, Saburo Muroga
1989	A	`conf`	SYLON-DREAM: a multi-level network synthesizer. ICCAD Kuang-Chien Chen, Saburo Muroga
1988	A	`conf`	Input assignment algorithm for decoded-PLAs with multi-input decoders. ICCAD Kuang-Chien Chen, Saburo Muroga