Kuan Zhou - RankMe

25 papers A 3B 3C 1Journal 6Unranked 12

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Self-sustainable chaotic dynamics of a liquid crystal elastomer pendulum in radial linear temperature fields. Commun. Nonlinear Sci. Numer. Simul. Peibao Xu, Kuan Zhou, Xin Sun, Kai Li
2024	B	`conf`	AAGF: An Efficient Transformer With Mix-Features For Visual Place Recognition. ICIP Kuan Zhou, Zhenyu Xu, Qieshi Zhang, Jun Cheng, Ziliang Ren, Xiangyang Gao
2019	—	`conf`	Dynamic Block Size Adjustment and Workload Balancing Strategy Based on CPU-GPU Heterogeneous Platform. ISPA/BDCloud/SocialCom/SustainCom Juan Fang, Kuan Zhou, Chen Tan, Hui Zhao
2015	J	`jnl`	High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology. Proc. IEEE Mitchell R. LeRoy, Srikumar Raman, Michael Chu, Jin Woo Kim, Jong-Ru Guo, Kuan Zhou, Chao You, Ryan Clarke, Bryan S. Goda, John F. McDonald
2011	—	`conf`	Iono-neuromorphic implementation of spike-timing-dependent synaptic plasticity. EMBC Yicong Meng, Kuan Zhou, Joshua J. C. Monzon, Chi-Sang Poon
2011	—	`conf`	On-chip dynamic programming networks using 3D-TSV integration. ICSAMOS Ra'ed Al-Dujaily, Terrence S. T. Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alexandre Yakovlev, Chi-Sang Poon
2010	—	`conf`	A 10B 200MHz pipeline ADC with minimal feedback penalty and 0.35pJ/conversion-step. SoCC Gang Chen, Yifei Luo, Jiayin Tian, Kuan Zhou
2009	—	`conf`	A picosecond TDC architecture for multiphase PLLs. ACM Great Lakes Symposium on VLSI Yifei Luo, Gang Chen, Kuan Zhou
2009	J	`jnl`	Impact of Deep-Trench-Isolation-Sharing Techniques on Ultrahigh-Speed Digital Systems. IEEE Trans. Circuits Syst. II Express Briefs Kuan Zhou, John F. McDonald
2006	C	`conf`	Triple-rail MOS current mode logic for high-speed self-timed pipeline applications. ISCAS Kuan Zhou, Yifei Luo, Sizhong Chen, Allen Drake, John F. McDonald, Tong Zhang
2005	J	`jnl`	A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC. Integr. Jong-Ru Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald
2005	J	`jnl`	A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block. Microprocess. Microsystems Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Peter F. Curran, Kuan Zhou, Bryan S. Goda, John F. McDonald
2005	—	`conf`	Multi-GHz SiGe design methodologies for reconfigurable computing. ACM Great Lakes Symposium on VLSI Kuan Zhou, John F. McDonald
2005	J	`jnl`	Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques. J. Circuits Syst. Comput. Kuan Zhou, Jong-Ru Guo, Chao You, John Mayega, Russell P. Kraft, T. Zhang, John F. McDonald, Bryan S. Goda
2004	—	`conf`	The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA. ACM Great Lakes Symposium on VLSI Jong-Ru Guo, Chao You, Peter F. Curran, Michael Chu, Kuan Zhou, Jiedong Diao, A. George, Russell P. Kraft, John F. McDonald
2004	A	`conf`	The gigahertz FPGA: design consideration and applications. FPGA Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald
2003	—	`conf`	3D direct vertical interconnect microprocessors test vehicle. ACM Great Lakes Symposium on VLSI John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald, Russell P. Kraft
2003	—	`conf`	A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology. ACM Great Lakes Symposium on VLSI Chao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou, Michael Chu, John F. McDonald
2003	—	`conf`	A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA. Engineering of Reconfigurable Systems and Algorithms Jong-Ru Guo, Chao You, Michael Chu, Kuan Zhou, Young Uk Yim, Robert W. Heikaus, Russell P. Kraft, John F. McDonald
2003	A	`conf`	A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme. FPGA Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald, Russell P. Kraft, Bryan S. Goda
2003	A	`conf`	A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology. FPGA Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald
2003	B	`conf`	Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory. FPL Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Robert W. Heikaus, Okan Erdogan, Peter F. Curran, Bryan S. Goda, Kuan Zhou, John F. McDonald
2002	B	`conf`	Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques. FPL Channakeshav, Kuan Zhou, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonald
2002	—	`conf`	Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic. Evolvable Hardware Channakeshav, Kuan Zhou, Russell P. Kraft, John F. McDonald
2002	—	`conf`	Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes. FPT Kuan Zhou, Channakeshav, Michael Chu, Jong-Ru Guo, S.-C. Liu, Russell P. Kraft, Chao You, John F. McDonald