Kuan-Yu Chen

24 papers A* 6A 3B 2C 1Journal 8Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET.
IEEE J. Solid State Circuits
Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw
2025 J jnl
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis.
Commun. ACM
Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Mohammad Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2025 A* conf
Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design.
HPCA
Haojie Ye, Yuchen Xia, Yuhan Chen, Kuan-Yu Chen, Yichao Yuan, Shuwen Deng, Baris Kasikci, Trevor N. Mudge, Nishil Talati
2024 J jnl
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication.
ACM Trans. Reconfigurable Technol. Syst.
Kuan-Yu Chen, Thomas Mason Nelson, Alireza Khadem, Morteza Fayazi, Sanjay Sri Vallabh Singapuram, Ronald G. Dreslinski, Nishil Talati, Hun-Seok Kim, David T. Blaauw
2024 J jnl
FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs).
IEEE Des. Test
Anish Krishnakumar, Hanguang Yu, Tutu Ajayi, A. Alper Goksoy, Vishrut Pandey, Joshua Mack, Md Sahil Hassan, Kuan-Yu Chen, Chaitali Chakrabarti, Daniel W. Bliss, Ali Akoglu, Hun-Seok Kim, Ronald G. Dreslinski, David T. Blaauw, Ümit Y. Ogras
2024 A conf
HypR: A comprehensive study for ASR hypothesis revising with a reference corpus.
INTERSPEECH
Yiwei Wang, Ke-Han Lu, Kuan-Yu Chen
2024 J jnl
Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design.
CoRR
Haojie Ye, Yuchen Xia, Yuhan Chen, Kuan-Yu Chen, Yichao Yuan, Shuwen Deng, Baris Kasikci, Trevor N. Mudge, Nishil Talati
2024 A conf
ParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications.
ISLPED
Seungkyu Choi, Huanshihong Deng, Kuan-Yu Chen, Yufan Yue, David T. Blaauw, Hun-Seok Kim
2023 A* conf
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis.
ISCA
Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2022 — conf
A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.
VLSI Technology and Circuits
Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw
2022 — conf
A Long-Range Narrowband RF Localization System with a Crystal-Less Frequency-Hopping Receiver.
ISSCC
Chien-Wei Tseng, Demba Komma, Kuan-Yu Chen, Rohit Rothe, Zhen Feng, Makoto Yasuda, Masaru Kawaminami, Hun-Seok Kim, David T. Blaauw
2022 C conf
Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor.
ISCAS
Daniel W. Bliss, Tutu Ajayi, Ali Akoglu, Ilkin Aliyev, Toygun Basaklar, Leul Belayneh, David T. Blaauw, John S. Brunhaver, Chaitali Chakrabarti, Liangliang Chang, Kuan-Yu Chen, Ming-Hung Chen, Xing Chen, Alex R. Chiriyath, Alhad Daftardar, Ronald G. Dreslinski, Arindam Dutta, Allen-Jasmin Farcas, Yukang Fu, A. Alper Goksoy, Xin He, Md Sahil Hassan, Andrew Herschfelt, Jacob Holtom, Hun-Seok Kim, A. N. Krishnakumar, Yang Li, Owen Ma, Joshua Mack, Saurav Mallik, Sumit K. Mandal, Radu Marculescu, Brittany M. McCall, Trevor N. Mudge, Ümit Y. Ogras, Vishrut Pandey, Saquib Ahmad Siddiqui, Yu-Hsiu Sun, Adarsh A. Venkataramani, Xiangdong Wei, B. R. Willis, Hanguang Yu, Yufan Yue
2022 B conf
Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems.
PACT
Leul Belayneh, Haojie Ye, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati
2022 A* conf
MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows.
ISCA
Siying Feng, Xin He, Kuan-Yu Chen, Liu Ke, Xuan Zhang, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2022 A* conf
Mint: An Accelerator For Mining Temporal Motifs.
MICRO
Nishil Talati, Haojie Ye, Sanketh Vedula, Kuan-Yu Chen, Yuhan Chen, Daniel Liu, Yichao Yuan, David T. Blaauw, Alex M. Bronstein, Trevor N. Mudge, Ronald G. Dreslinski
2022 A* conf
NDMiner: accelerating graph pattern mining using near data processing.
ISCA
Nishil Talati, Haojie Ye, Yichen Yang, Leul Belayneh, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2022 B conf
Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor.
PACT
Xin He, Kuan-Yu Chen, Siying Feng, Hun-Seok Kim, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge
2022 J jnl
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
IEEE J. Solid State Circuits
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2021 A* conf
SquiggleFilter: An Accelerator for Portable Virus Detection.
MICRO
Timothy Dunn, Harisankar Sadasivan, Jack Wadden, Kush Goliya, Kuan-Yu Chen, David T. Blaauw, Reetuparna Das, Satish Narayanasamy
2021 — conf
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
VLSI Circuits
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2021 J jnl
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
CoRR
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2020 J jnl
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits
Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
2020 A conf
Sparse-TPU: adapting systolic arrays for sparse matrices.
ICS
Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Kuan-Yu Chen, Ronald G. Dreslinski, Trevor N. Mudge
2019 — conf
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
VLSI Circuits
Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski