Krzysztof S. Berezowski

14 papers A 2C 2Misc 1Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2014 J jnl
Calibration of RO-based temperature sensors for a toolset for measuring thermal behavior of FPGA devices.
Microelectron. J.
Pawel Weber, Maciej Zagrabski, Bartosz Wojciechowski, Maciej Nikodem, Krzysztof Kepa, Krzysztof S. Berezowski
2013 — conf
Empirical Recovery of Input Nonlinearity in Distributed Element Models.
ALCOSP
Przemyslaw Sliwinski, Krzysztof S. Berezowski, Pawel Wachel, Gilles Sicard, Laurent Fesquet
2013 J jnl
Fast and accurate thermal modeling and simulation of manycore processors and workloads.
Microelectron. J.
Bartosz Wojciechowski, Krzysztof S. Berezowski, Piotr Patronik, Janusz Biernat
2012 — conf
Design of an RNS reverse converter for a new five-moduli special set.
ACM Great Lakes Symposium on VLSI
Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava
2011 A conf
Fast and energy-efficient constant-coefficient FIR filters using residue number system.
ISLPED
Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava
2011 J jnl
Identification of Threshold Functions and Synthesis of Threshold Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tejaswi Gowda, Sarma B. K. Vrudhula, Niranjan Kulkarni, Krzysztof S. Berezowski
2010 — conf
A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS.
ISVLSI
Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula
2010 — conf
Out-of-order issue logic using sorting networks.
ACM Great Lakes Symposium on VLSI
Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski
2009 Misc conf
Exploiting residue number system for power-efficient digital signal processing in embedded processors.
CASES
Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak
2008 A conf
Analytical results for design space exploration of multi-core processors employing thread migration.
ISLPED
Ravishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski
2007 — conf
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices.
ISMVL
Krzysztof S. Berezowski, Sarma B. K. Vrudhula
2007 J jnl
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices.
J. Multiple Valued Log. Soft Comput.
Krzysztof S. Berezowski, Sarma B. K. Vrudhula
2005 C conf
Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series.
DSD
Krzysztof S. Berezowski, Sarma B. K. Vrudhula
2001 C conf
Transistor Chainning with Integrated Dynamic Folding for 1-D Leaf Cell Synthesis.
DSD
Krzysztof S. Berezowski