Krishnaswamy Nagaraj

30 papers B 1Journal 24Unranked 5

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	Fault-based Built-in Self-test and Evaluation of Phase Locked Loops. ACM Trans. Design Autom. Electr. Syst. Mehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev
2019	B	`conf`	Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection. ETS Mehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev
2017	—	`conf`	A 12-/14-bit, 4/2MSPS, 0.085mm CICC Joonsung Park, Krishnaswamy Nagaraj, Mikel Ash, Ajay Kumar
2016	—	`conf`	An oxide electrothermal filter in standard CMOS. IEEE SENSORS Lorenzo Pedala, Ugur Sonmez, Fabio Sebastiano, Kofi A. A. Makinwa, Krishnaswamy Nagaraj, Joonsung Park
2015	J	`jnl`	An Embedded 65 nm CMOS Remote Temperature Sensor With Digital Beta Correction and Series Resistance Cancellation Achieving an Inaccuracy of 0.4 IEEE J. Solid State Circuits Xiao Pu, Mikel Ash, Krishnaswamy Nagaraj, Joonsung Park, Steve Vu, Paul Kimelman, Sean de la Haye
2014	—	`conf`	A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC. MWSCAS Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan
2014	J	`jnl`	Corrections to "Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference". IEEE Trans. Circuits Syst. II Express Briefs Xiao Pu, Ajay Kumar, Krishnaswamy Nagaraj
2013	J	`jnl`	Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun
2012	J	`jnl`	A Novel fractional-n PLL Based on a Simple Reference Multiplier. J. Circuits Syst. Comput. Xiao Pu, Krishnaswamy Nagaraj, Jacob A. Abraham, Axel Thomsen
2012	J	`jnl`	Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference. IEEE Trans. Circuits Syst. II Express Briefs Xiao Pu, Ajay Kumar, Krishnaswamy Nagaraj
2011	J	`jnl`	A Two-Stage ADC Architecture With VCO-Based Second Stage. IEEE Trans. Circuits Syst. II Express Briefs Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan
2007	J	`jnl`	Message from the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits Krishnaswamy Nagaraj
2007	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Krishnaswamy Nagaraj
2007	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Krishnaswamy Nagaraj
2007	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Krishnaswamy Nagaraj
2007	J	`jnl`	New Associate Editors. IEEE J. Solid State Circuits Krishnaswamy Nagaraj
2005	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Krishnaswamy Nagaraj
2005	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Krishnaswamy Nagaraj
2005	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Krishnaswamy Nagaraj
2004	J	`jnl`	Editorial. IEEE J. Solid State Circuits Krishnaswamy Nagaraj
2001	—	`conf`	A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. CICC Gennady Feygin, Krishnaswamy Nagaraj, Ranjan Chattopadhyay, R. Herrera, I. Papantonopoulos, David A. Martin, P. Wu, Shanthi Pavan
2000	J	`jnl`	A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. IEEE J. Solid State Circuits Krishnaswamy Nagaraj, David A. Martin, Mark A. Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan
2000	J	`jnl`	Widely programmable high-frequency continuous-time filters in digital CMOS technology. IEEE J. Solid State Circuits Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj
1999	—	`conf`	Modeling of accumulation MOS capacitors for analog design in digital VLSI processes. ISCAS (6) Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj
1997	J	`jnl`	A 160-MHz analog equalizer for magnetic disk read Channel. IEEE J. Solid State Circuits Sami Kiriaki, T. Lakshmi Viswanathan, Gennady Feygin, Robert Bogdan Staszewski, Richard Pierson, Bill Krenik, Michiel de Wit, Krishnaswamy Nagaraj
1997	J	`jnl`	A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers. IEEE J. Solid State Circuits Krishnaswamy Nagaraj, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis, Robert G. Renninger
1995	J	`jnl`	A low supply voltage high PSRR voltage reference in CMOS process. IEEE J. Solid State Circuits Khong-Meng Tham, Krishnaswamy Nagaraj
1991	J	`jnl`	A baseband codec for digital cellular telephony. IEEE J. Solid State Circuits Kadaba R. Lakshmikumar, David W. Green, Krishnaswamy Nagaraj, King-Hon Lau, Oscar E. Agazzi, Jeffrey R. Barner, Reza S. Shariatdoust, Gene A. Wilson, Tuan N. Le, M. R. Dwarakanath, Jacques G. Ruch, Jit Kumar, Timo Ali-Vehmas, Jouko J. Junkkari, Lauri Siren
1990	J	`jnl`	Sampled-data and continuous-time squarers in MOS technology. IEEE J. Solid State Circuits John M. Khoury, Krishnaswamy Nagaraj, James M. Trosino
1989	J	`jnl`	Large-swing CMOS buffer amplifier. IEEE J. Solid State Circuits Krishnaswamy Nagaraj