Krishnamurthy Soumyanath

41 papers A 3Journal 16Unranked 22

Year	Rank	Type	Title / Venue / Authors
2013	J	`jnl`	A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver. IEEE J. Solid State Circuits Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Khoa Minh Nguyen, Hyung-Jin Lee, Ashoke Ravi, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Satish Venkatesan, Durgesh Srivastava, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Sunder Ramamurthy, Raj Yavatkar, Krishnamurthy Soumyanath
2012	—	`conf`	32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver. ISSCC Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Durgesh Srivastava, Satish Venkatesan, Hyung-Jin Lee, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Krishnamurthy Soumyanath, Sunder Ramamurthy
2012	—	`conf`	A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS. ISSCC Y. William Li, Carlos Ornelas, Hyung Seok Kim, Hasnain Lakdawala, Ashoke Ravi, Krishnamurthy Soumyanath
2011	—	`conf`	A 2.5GHz 32nm 0.35mm ISSCC Chang-Tsung Fu, Hasnain Lakdawala, Stewart S. Taylor, Krishnamurthy Soumyanath
2011	J	`jnl`	A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application. IEEE J. Solid State Circuits Hongtao Xu, Yorgos Palaskas, Ashoke Ravi, Masoud Sajadieh, Mohammed A. El-Tanani, Krishnamurthy Soumyanath
2010	—	`conf`	A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application. ESSCIRC Hongtao Xu, Yorgos Palaskas, Ashoke Ravi, Krishnamurthy Soumyanath
2009	J	`jnl`	A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process. IEEE J. Solid State Circuits Hasnain Lakdawala, Y. William Li, Arijit Raychowdhury, Greg Taylor, Krishnamurthy Soumyanath
2009	—	`conf`	A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS. ISSCC Y. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, Krishnamurthy Soumyanath
2009	—	`conf`	A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS. ISSCC Erkan Alpman, Hasnain Lakdawala, L. Richard Carley, Krishnamurthy Soumyanath
2009	—	`conf`	A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS. CICC Tawfiq Musah, Sunwoo Kwon, Hasnain Lakdawala, Krishnamurthy Soumyanath, Un-Ku Moon
2009	J	`jnl`	A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS. IEEE J. Solid State Circuits Jeffrey S. Walling, Hasnain Lakdawala, Yorgos Palaskas, Ashoke Ravi, Ofir Degani, Krishnamurthy Soumyanath, David J. Allstot
2008	—	`conf`	A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution. ESSCIRC Hiroyuki Ito, Hasnain Lakdawala, Ashoke Ravi, Stefano Pellerano, Rick Ruby, Krishnamurthy Soumyanath, Kazuya Masu
2008	—	`conf`	A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation. ISSCC Jeffrey S. Walling, Hasnain Lakdawala, Yorgos Palaskas, Ashoke Ravi, Ofir Degani, Krishnamurthy Soumyanath, David J. Allstot
2008	—	`conf`	A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX Receivers. ISSCC Pukar Malla, Hasnain Lakdawala, Kevin T. Kornegay, Krishnamurthy Soumyanath
2008	—	`conf`	A 3.6GHz, 16mW ΣΔ DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS. ESSCIRC Parmoon Seddighrad, Ashoke Ravi, Masoud Sajadieh, Hasnain Lakdawala, Krishnamurthy Soumyanath
2008	J	`jnl`	A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS. IEEE J. Solid State Circuits Stefano Pellerano, Yorgos Palaskas, Krishnamurthy Soumyanath
2008	J	`jnl`	Desensitized CMOS Low-Noise Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. Gaurab Banerjee, Krishnamurthy Soumyanath, David J. Allstot
2007	—	`conf`	A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS. ESSCIRC Stefano Pellerano, Yorgos Palaskas, Krishnamurthy Soumyanath
2006	J	`jnl`	A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${\rm P}_{\rm 1dB}$ Power Amplifiers in 90-nm CMOS. IEEE J. Solid State Circuits Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph E. Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Nati Dinur, Stewart S. Taylor, Krishnamurthy Soumyanath
2006	J	`jnl`	A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process. IEEE J. Solid State Circuits Yorgos Palaskas, Stewart S. Taylor, Stefano Pellerano, Ian A. Rippke, Ralph E. Bishop, Ashoke Ravi, Hasnain Lakdawala, Krishnamurthy Soumyanath
2006	—	`conf`	A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS. ISSCC Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph E. Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Stewart S. Taylor, Krishnamurthy Soumyanath
2006	J	`jnl`	A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion. IEEE J. Solid State Circuits Mostafa Elmala, Jeyanandh Paramesh, Krishnamurthy Soumyanath
2005	—	`conf`	A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction. CICC Yorgos Palaskas, Stewart S. Taylor, Stefano Pellerano, Ian A. Rippke, Ralph E. Bishop, Ashoke Ravi, Hasnain Lakdawala, Krishnamurthy Soumyanath
2005	—	`conf`	A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS. ESSCIRC Charles T. Peach, Ashoke Ravi, Rosie Bishop, Krishnamurthy Soumyanath, David J. Allstot
2005	—	`conf`	A 90-nm MOS-only 3-11GHz transmitter for UWB. CICC Yorgos Palaskas, Ralph E. Bishop, Ashoke Ravi, Krishnamurthy Soumyanath
2005	J	`jnl`	A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity. IEEE J. Solid State Circuits Jeyanandh Paramesh, Ralph Bishop, Krishnamurthy Soumyanath, David J. Allstot
2004	—	`conf`	8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3 CICC Ashoke Ravi, Ralph E. Bishop, L. Richard Carley, Krishnamurthy Soumyanath
2004	—	`conf`	Desensitized design of MOS low noise amplifiers by R ICECS Gaurab Banerjee, David T. Becher, Celia Hung, Krishnamurthy Soumyanath, David J. Allstot
2004	—	`conf`	Measurement and modeling of noise parameters for desensitized low noise amplifiers. CICC Gaurab Banerjee, David T. Becher, Celia Hung, David J. Allstot, Krishnamurthy Soumyanath
2004	J	`jnl`	Measurements and analysis of SER-tolerant latch in a 90-nm dual-V IEEE J. Solid State Circuits Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2003	—	`conf`	17GHz and 24GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18μm logic CMOS technology. ESSCIRC Luiz M. Franca-Neto, Bradley A. Bloechel, Krishnamurthy Soumyanath
2003	—	`conf`	Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. CICC Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2002	J	`jnl`	5-GHz 32-bit integer execution core in 130-nm dual-V IEEE J. Solid State Circuits Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar
2002	J	`jnl`	A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. IEEE J. Solid State Circuits Ram K. Krishnamurthy, Atila Alvandpour, Ganesh Balamurugan, Naresh R. Shanbhag, Krishnamurthy Soumyanath, Shekhar Y. Borkar
2002	J	`jnl`	A sub-130-nm conditional keeper technique. IEEE J. Solid State Circuits Atila Alvandpour, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Y. Borkar
2001	A	`conf`	A low-leakage dynamic multi-ported register file in 0.13mm CMOS. ISLPED Atila Alvandpour, Ram Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Borkar
2001	—	`conf`	Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. ACM Great Lakes Symposium on VLSI Ram Krishnamurthy, Mark A. Anders, Krishnamurthy Soumyanath, Shekhar Borkar
2001	J	`jnl`	Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends. IEEE J. Solid State Circuits Sanu K. Mathew, Ram K. Krishnamurthy, Mark A. Anders, Rafael Rios, Kaizad R. Mistry, Krishnamurthy Soumyanath
2000	A	`conf`	Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. ITC Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De
2000	A	`conf`	Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). ISLPED Naresh R. Shanbhag, Krishnamurthy Soumyanath, Samuel Martin
1999	J	`jnl`	Accurate on-chip interconnect evaluation: a time-domain technique. IEEE J. Solid State Circuits Krishnamurthy Soumyanath, Shekhar Borkar, Chunyan Zhou, Bradley A. Bloechel