Krishna Chakravadhanula

17 papers A 11Misc 1Journal 1Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Pseudo-Random Low Power Built In Self Test. ITC Dale Meehl, Sameer Chillarige, Bharath Nandakumar, Carl Wisnesky, Krishna Chakravadhanula
2022	A	`conf`	PPA Optimization of Test Points in Automotive Designs. ITC Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran
2019	A	`conf`	Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications. ITC Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula
2018	A	`conf`	Improving Diagnosis Resolution and Performance at High Compression Ratios. ITC Sameer Chillarige, Atul Chhabra, Anil Malik, Bharath Nandakumar, Joe Swenton, Krishna Chakravadhanula
2017	A	`conf`	Advancing test compression to the physical dimension. ITC Krishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox
2017	A	`conf`	High throughput multiple device diagnosis system. ITC Sameer Chillarige, Anil Malik, Sharjinder Singh, Joe Swenton, Krishna Chakravadhanula
2015	—	`conf`	A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures. NATW Sameer Chillarige, S. Virdi, Anil Malik, Krishna Chakravadhanula, Vivek Chickermane, Joe Swenton, G. Vandling
2014	A	`conf`	Efficient testing of hierarchical core-based SOCs. ITC Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
2014	Misc	`conf`	Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. VLSID Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula
2013	A	`conf`	SmartScan - Hierarchical test compression for pin-limited low power designs. ITC Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj
2010	A	`conf`	Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
2009	J	`jnl`	Automating IEEE 1500 Core Test—An EDA Perspective. IEEE Des. Test Comput. Krishna Chakravadhanula, Vivek Chickermane
2009	A	`conf`	Capture power reduction using clock gating aware test generation. ITC Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang
2009	—	`conf`	Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman
2008	A	`conf`	A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. ITC Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula
2008	—	`conf`	Test Generation for State Retention Logic. ATS Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor
2007	—	`conf`	Low Power Reduced Pin Count Test Methodology. ATS Krishna Chakravadhanula, Nitin Parimi, Brian Foutz, Bing Li, Vivek Chickermane