Kris Tiri

31 papers A* 5A 6B 2C 1Misc 1Journal 11Unranked 4
YearRankTypeTitle / Venue / Authors
2010 — ch.
Side-Channel Resistant Circuit Styles and Associated IC Design Flow.
Secure Integrated Circuits and Systems
Kris Tiri
2007 J jnl
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
CoRR
Kris Tiri, Ingrid Verbauwhede
2007 A* conf
An Analytical Model for Time-Driven Cache Attacks.
FSE
Kris Tiri, Onur Aciiçmez, Michael Neve, Flemming Andersen
2007 J jnl
Design Method for Constant Power Consumption of Differential Logic Circuits
CoRR
Kris Tiri, Ingrid Verbauwhede
2007 A conf
Masking and Dual-Rail Logic Don't Add Up.
CHES
Patrick Schaumont, Kris Tiri
2007 J jnl
On the complexity of side-channel attacks on AES-256 - methodology and quantitative results on cache attacks.
IACR Cryptol. ePrint Arch.
Michael Neve, Kris Tiri
2007 A* conf
Side-Channel Attack Pitfalls.
DAC
Kris Tiri
2006 J jnl
A digital design flow for secure integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kris Tiri, Ingrid Verbauwhede
2006 J jnl
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks.
IEEE J. Solid State Circuits
David D. Hwang, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
2006 B conf
Changing the Odds Against Masked Logic.
Selected Areas in Cryptography
Kris Tiri, Patrick Schaumont
2006 J jnl
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2006 J jnl
Securing Embedded Systems.
IEEE Secur. Priv.
David Hwang, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede
2006 — conf
Side-Channel Leakage Tolerant Architectures.
ITNG
Kris Tiri, Patrick Schaumont, Ingrid Verbauwhede
2005 — conf
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology.
ACM Great Lakes Symposium on VLSI
Alireza Hodjat, David Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede
2005 A conf
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs.
DATE
Kris Tiri, Ingrid Verbauwhede
2005 A* conf
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.
DAC
Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
2005 A conf
Design Method for Constant Power Consumption of Differential Logic Circuits.
DATE
Kris Tiri, Ingrid Verbauwhede
2005 A conf
Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.
CHES
Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
2005 A* conf
Simulation models for side-channel information leaks.
DAC
Kris Tiri, Ingrid Verbauwhede
2004 J jnl
A Dynamic and Differential CMOS Logic Style to Resist Power and Timing Attacks on Security IC's.
IACR Cryptol. ePrint Arch.
Kris Tiri, Ingrid Verbauwhede
2004 A conf
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation.
DATE
Kris Tiri, Ingrid Verbauwhede
2004 J jnl
Charge Recycling Sense Amplifier Based Logic: Securing Low Power Security IC's against Differential Power Analysis.
IACR Cryptol. ePrint Arch.
Kris Tiri, Ingrid Verbauwhede
2004 — conf
Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis].
ESSCIRC
Kris Tiri, Ingrid Verbauwhede
2004 J jnl
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.
IEEE J. Solid State Circuits
Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2004 Misc conf
Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques.
CASES
Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede
2004 C conf
Place and Route for Secure Standard Cell Design.
CARDIS
Kris Tiri, Ingrid Verbauwhede
2004 B conf
Secure Logic Synthesis.
FPL
Kris Tiri, Ingrid Verbauwhede
2004 J jnl
Synthesis of Secure FPGA Implementations.
IACR Cryptol. ePrint Arch.
Kris Tiri, Ingrid Verbauwhede
2003 — conf
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.
ESSCIRC
Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2003 A conf
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology.
CHES
Kris Tiri, Ingrid Verbauwhede
2002 A* conf
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.
DAC
Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen