Kozo Kinoshita

119 papers A* 4A 15B 1C 1Misc 9Journal 52Unranked 37

Year	Rank	Type	Title / Venue / Authors
2013	J	`jnl`	SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Kozo Kinoshita
2010	B	`conf`	Current-based testable design of level shifters in liquid crystal display drivers. ETS Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita
2008	J	`jnl`	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2007	J	`jnl`	A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
2007	J	`jnl`	A statistical error model for image sensors and its testing. Syst. Comput. Jpn. Hideyuki Ichihara, Toshimasa Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita
2006	Misc	`conf`	A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
2006	J	`jnl`	A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Trans. Inf. Syst. Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2006	J	`jnl`	A Per-Test Fault Diagnosis Method Based on the IEICE Trans. Inf. Syst. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
2005	J	`jnl`	Fault Diagnosis of Physical Defects Using Unknown Behavior Model. J. Comput. Sci. Technol. Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
2005	A	`conf`	Low-capture-power test generation for scan-based at-speed testing. ITC Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005	J	`jnl`	On Design for I IEICE Trans. Inf. Syst. Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
2005	Misc	`conf`	On Low-Capture-Power Test Generation for Scan Testing. VTS Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005	J	`jnl`	Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. J. Electron. Test. Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
2004	—	`conf`	On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. DELTA Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
2004	A	`conf`	On per-test fault diagnosis using the X-fault model. ICCAD Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2003	—	`conf`	A BIST Circuit for IDDQ Tests. Asian Test Symposium Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita
2003	Misc	`conf`	Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. VLSI Design Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa
2003	—	`conf`	Fault Diagnosis for Physical Defects of Unknown Behaviors. Asian Test Symposium Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
2003	—	`conf`	Reducing Scan Shifts Using Folding Scan Trees. Asian Test Symposium Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
2002	J	`jnl`	Built-in Self-Test for crosstalk faults in a digital VLSI. Syst. Comput. Jpn. Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita
2002	—	`conf`	Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. Asian Test Symposium Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita
2002	—	`conf`	Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits. DELTA Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita
2002	J	`jnl`	Foreword. J. Electron. Test. Kozo Kinoshita
2002	A	`conf`	On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
2001	—	`conf`	Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits. Asian Test Symposium Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita
2001	—	`conf`	IDDQ Sensing Technique for High Speed IDDQ Testing. Asian Test Symposium Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita
2000	—	`conf`	A high-speed IDDQ sensor implementation. Asian Test Symposium Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita
2000	J	`jnl`	Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electron. Test. Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
2000	J	`jnl`	Compaction of IDDQ Test Sequence Using Reassignment Method. J. Electron. Test. Toshiyuki Maeda, Kozo Kinoshita
2000	—	`conf`	Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
2000	—	`conf`	Memory reduction of I Asian Test Symposium Toshiyuki Maeda, Kozo Kinoshita
2000	A	`conf`	Precise test generation for resistive bridging faults of CMOS combinational circuits. ITC Toshiyuki Maeda, Kozo Kinoshita
2000	—	`conf`	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. Asian Test Symposium Arabi Keshk, Yukiya Miura, Kozo Kinoshita
2000	J	`jnl`	Static test compaction for IDDQ testing of bridging faults in sequential circuits. Syst. Comput. Jpn. Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita
2000	Misc	`conf`	Test Transformation to Improve Compaction by Statistical Encoding. VLSI Design Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
2000	—	`conf`	Test sequence compaction for sequential circuits with reset states. Asian Test Symposium Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita
1999	—	`conf`	Compaction of IDDQ test sequence using reassignment method. ETW Toshiyuki Maeda, Kozo Kinoshita
1999	Misc	`conf`	Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. VLSI Design Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
1999	—	`conf`	Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
1999	—	`conf`	IDDQ Current Dependency on Test Vectors and Bridging Resistance. Asian Test Symposium Arabi Keshk, Kozo Kinoshita, Yukiya Miura
1999	—	`conf`	On Test Generation with A Limited Number of Tests. Great Lakes Symposium on VLSI Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
1999	—	`conf`	On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
1999	—	`conf`	Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. Asian Test Symposium Arabi Keshk, Kozo Kinoshita, Yukiya Miura
1998	—	`conf`	A High-Speed IDDQ Sensor for Low-Voltage ICs. Asian Test Symposium Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita
1998	—	`conf`	An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. Asian Test Symposium Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita
1998	—	`conf`	Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA. Asian Test Symposium Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita
1998	—	`conf`	Design for Diagnosability of CMOS Circuits. Asian Test Symposium Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
1998	—	`conf`	Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. Asian Test Symposium Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
1998	Misc	`conf`	Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. VTS Hiroyuki Yotsuyanagi, Kozo Kinoshita
1997	Misc	`conf`	A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. VLSI Design Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
1997	J	`jnl`	A diagnosis method for single logic design errors in gate-level combinational circuits. Syst. Comput. Jpn. Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita
1997	—	`conf`	An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits. Asian Test Symposium Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita
1997	—	`conf`	Design of partially parallel scan chain. ED&TC Yoshinobu Higami, Kozo Kinoshita
1997	J	`jnl`	I Syst. Comput. Jpn. Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita
1997	—	`conf`	On Acceleration of Logic Circuits Optimization Using Implication Relations. Asian Test Symposium Hideyuki Ichihara, Kozo Kinoshita
1997	J	`jnl`	On invariant implication relations for removing partial circuits. Syst. Comput. Jpn. Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
1997	J	`jnl`	Synthesis of Sequential Circuits by Redundancy Removal and Retiming. J. Electron. Test. Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1996	—	`conf`	A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits. FTCS Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita
1996	—	`conf`	Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1995	J	`jnl`	Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis. IEICE Trans. Inf. Syst. Seiji Kajihara, Rikiya Nishigaya, Tetsuji Sumioka, Kozo Kinoshita
1995	J	`jnl`	Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1995	J	`jnl`	Efficient Guided-Probe Fault Location Method for Sequential Circuits. IEICE Trans. Inf. Syst. Xiaoqing Wen, Kozo Kinoshita, Hideo Tamamoto, Hiroshi Yokoyama
1995	J	`jnl`	Evaluation of the maximum number of switching gates for CMOS circuits. Syst. Comput. Jpn. Hiroaki Ueda, Kozo Kinoshita
1995	—	`conf`	Low power design and its testability. Asian Test Symposium Hiroaki Ueda, Kozo Kinoshita
1995	J	`jnl`	Partial scan design and test sequence generation based on reduced scan shift method. J. Electron. Test. Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1995	Misc	`conf`	Resynthesis for sequential circuits designed with a specified initial state. VTS Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1995	J	`jnl`	Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement. IEICE Trans. Inf. Syst. Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1995	—	`conf`	Synthesis for Testability by Sequential Redundancy Removal Using Retiming. FTCS Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1995	J	`jnl`	Test pattern generation for crosstalk faults considering the gate delay. Syst. Comput. Jpn. Noriyoshi Itazaki, Kozo Kinoshita, Hisao Naitoh
1995	—	`conf`	Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1995	J	`jnl`	Testing of IEICE Trans. Inf. Syst. Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita
1995	—	`conf`	Transistor leakage fault location with ZDDQ measurement. Asian Test Symposium Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita
1994	C	`conf`	A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. ISCAS Yukiya Miura, Sachio Naito, Kozo Kinoshita
1994	J	`jnl`	An approach to the analysis and detection of crosstalk faults in digital VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita
1994	Misc	`conf`	On compacting test sets by addition and removal of test vectors. VTS Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1994	A	`conf`	Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1993	A*	`conf`	Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. DAC Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1993	J	`jnl`	Design of testing circuit and test generation for built-in current testing. Syst. Comput. Jpn. Yukiya Miura, Yasushi Wada, Kozo Kinoshita
1993	J	`jnl`	Removal of redundancy in combinational circuits under classification of undetectable faults. Syst. Comput. Jpn. Seiji Kajihara, Kozo Kinoshita, Haruko Shiba
1993	A	`conf`	Test generation for multiple faults based on parallel vector pair analysis. ICCAD Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita
1992	J	`jnl`	A Testable Design of Logic Circuits under Highly Observable Condition. IEEE Trans. Computers Xiaoqing Wen, Kozo Kinoshita
1992	A	`conf`	Circuit Design for Built-in Current Testing. ITC Yukiya Miura, Kozo Kinoshita
1992	—	`conf`	Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults. FTCS Seiji Kajihara, Haruko Shiba, Kozo Kinoshita
1992	A	`conf`	Testable Designs of Sequential Circuits Under Highly Observable Condition. ITC Xiaoqing Wen, Kozo Kinoshita
1991	—	`conf`	An approach to the analysis and test of crosstalk faults in digital VLSI circuits. EURO-DAC Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita
1991	J	`jnl`	Stuck-open faults test generation for cmos combinational circuits. Syst. Comput. Jpn. Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita
1990	J	`jnl`	A built-in self-test algorithm for row/column pattern sensitive faults in RAMs. IEEE J. Solid State Circuits Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
1990	A	`conf`	A testable design of logic circuits under highly observable condition. ITC Xiaoqing Wen, Kozo Kinoshita
1990	J	`jnl`	Extended selection of switching target faults in CONT algorithm for test generation. J. Electron. Test. Yuzo Takamatsu, Kozo Kinoshita
1990	—	`conf`	Fault detection and diagnosis of k-UCP circuits under totally observable condition. FTCS Xiaoqing Wen, Kozo Kinoshita
1990	A	`conf`	On the evaluation of process-fault tolerance ability of CMOS integrated circuits. ITC Etienne Sicard, Kozo Kinoshita
1989	J	`jnl`	CONT: a concurrent test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuzo Takamatsu, Kozo Kinoshita
1989	A	`conf`	Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. ITC Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
1989	—	`conf`	Row/column pattern sensitive fault detection in RAMs via built-in self-test. FTCS Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
1989	J	`jnl`	Test pattern generation for circuits with tri-state modules by Z-algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Noriyoshi Itazaki, Kozo Kinoshita
1987	J	`jnl`	Built-In Self-Testing RAM: A Practical Alternative. IEEE Des. Test Kewal K. Saluja, Siew H. Sng, Kozo Kinoshita
1986	J	`jnl`	Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. IEEE Trans. Computers Kozo Kinoshita, Kewal K. Saluja
1986	A	`conf`	Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm. ITC Noriyoshi Itazaki, Kozo Kinoshita
1985	A	`conf`	A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. ITC Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita
1985	J	`jnl`	Design of Programmable Logic Arrays for Parallel Testing. Comput. Syst. Sci. Eng. C. Boswell, Kewal K. Saluja, Kozo Kinoshita
1985	J	`jnl`	Test Pattern Generation for API Faults in RAM. IEEE Trans. Computers Kewal K. Saluja, Kozo Kinoshita
1984	A	`conf`	Built-in Testing of Memory Using On-chip Compact Testing Scheme. ITC Kozo Kinoshita, Kewal K. Saluja
1983	J	`jnl`	An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. IEEE Trans. Computers Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara
1983	A	`conf`	Design of High-Level Test Language for Digital LSI. ITC Takuji Okamoto, Hiroyuki Shibata, Kozo Kinoshita
1983	A*	`conf`	Test generation for scan design circuits with tri-state modules and bidirectional terminals. DAC Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara
1981	J	`jnl`	A Design of Programmable Logic Arrays with Universal Tests. IEEE Trans. Computers Hideo Fujiwara, Kozo Kinoshita
1981	A*	`conf`	An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2. DAC Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita
1979	J	`jnl`	Conservative Logic Elements and Their Universality. IEEE Trans. Computers Tsutomu Sasao, Kozo Kinoshita
1979	J	`jnl`	On the Number of Fanout-Free Functions and Unate Cascade Functions. IEEE Trans. Computers Tsutomu Sasao, Kozo Kinoshita
1978	J	`jnl`	Cascade Realization of 3-Input 3-Output Conservative Logic Circuits. IEEE Trans. Computers Tsutomu Sasao, Kozo Kinoshita
1978	J	`jnl`	Connection Assignments for Probabilistically Diagnosable Systems. IEEE Trans. Computers Hideo Fujiwara, Kozo Kinoshita
1978	A*	`conf`	LORES - Logic Reorganization System. DAC Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita
1978	J	`jnl`	On the Computational Complexity of System Diagnosis. IEEE Trans. Computers Hideo Fujiwara, Kozo Kinoshita
1978	J	`jnl`	Realization of Minimum Circuits with Two-Input Conservative Logic Elements. IEEE Trans. Computers Tsutomu Sasao, Kozo Kinoshita
1978	J	`jnl`	Some Existence Theorems for Probabilistically Diagnosable Systems. IEEE Trans. Computers Hideo Fujiwara, Kozo Kinoshita
1976	J	`jnl`	On Magnetic Bubble Logic Circuits. IEEE Trans. Computers Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda
1975	J	`jnl`	Easily Testable Sequential Machines with Extra Inputs. IEEE Trans. Computers Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita
1974	J	`jnl`	Design of Diagnosable Sequential Machines Utilizing Extra Outputs. IEEE Trans. Computers Hideo Fujiwara, Kozo Kinoshita
1970	J	`jnl`	Sequential Machines Capable of Fault Diagnosis. IEEE Trans. Computers Shin-ichi Murakami, Kozo Kinoshita, Hiroshi Ozaki