Koyo Nitta

27 papers A 2B 1C 5Journal 12Unranked 6
YearRankTypeTitle / Venue / Authors
2025 C conf
Video Transfer Method Suitable for Object Detection in the Cloud.
ICCE
Mamoru Shirahase, Koyo Nitta, Yusuke Horishita, Yuya Omori, Daisuke Kobayashi, Ken Nakamura
2023 J jnl
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture.
IEICE Trans. Electron.
Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi
2023 J jnl
High-definition technology of AI inference scheme for object detection on edge/terminal.
IEICE Electron. Express
Hiroyuki Uzawa, Shuhei Yoshida, Yukou Iinuma, Saki Hatta, Daisuke Kobayashi, Yuya Omori, Yusuke Horishita, Ken Nakamura, Shuichi Takada, Hassan Toorabally, Koyo Nitta, Koji Yamazaki, Kimikazu Sano
2022 — conf
An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture.
COOL CHIPS
Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi
2022 — conf
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization.
MWSCAS
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano
2021 J jnl
A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation.
IEICE Trans. Commun.
Hiroyuki Uzawa, Kazuhiko Terada, Koyo Nitta
2021 J jnl
FPGA-based network microburst analysis system with efficient packet capturing.
JOCN
Shuhei Yoshida, Yuta Ukon, Shoko Ohteru, Hiroyuki Uzawa, Namiko Ikeda, Koyo Nitta
2021 J jnl
Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems.
IEICE Trans. Commun.
Saki Hatta, Nobuyuki Tanaka, Hiroyuki Uzawa, Koyo Nitta
2020 — conf
FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing.
ASAP
Shuhei Yoshida, Yuta Ukon, Shoko Ohteru, Hiroyuki Uzawa, Namiko Ikeda, Koyo Nitta
2020 J jnl
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.
IEICE Trans. Electron.
Ken Nakamura, Daisuke Kobayashi, Yuya Omori, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki
2020 J jnl
Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture.
IEICE Trans. Commun.
Yuta Ukon, Koji Yamazaki, Koyo Nitta
2019 — conf
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.
COOL CHIPS
Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu
2018 J jnl
A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K.
IEEE Trans. Very Large Scale Integr. Syst.
Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu
2018 C conf
Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane.
HPSR
Koji Yamazaki, Yuta Ukon, Shuhei Yoshida, Saki Hatta, Yusuke Sekihara, Shoko Ohteru, Tomoaki Kawamura, Takahiro Hatano, Koyo Nitta, Akihiko Miyazaki
2018 C conf
Video Service Function Chaining with a Real-time Packet Reordering Circuit.
ISCAS
Yuta Ukon, Koji Yamazaki, Koyo Nitta
2015 — —
Motion Estimation and Compensation Hardware Architecture with Hierarchy of Flexibility in Video Encoder LSIs.
Koyo Nitta
2015 — conf
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure.
Hot Chips Symposium
Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu
2015 — conf
Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability.
VLSIC
Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu
2013 B conf
Residue role assignment based transform partition predetermination on HEVC.
ICIP
Jia Su, Koyo Nitta, Mitsuo Ikeda, Atsushi Shimizu
2012 J jnl
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures.
IEICE Trans. Electron.
Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma
2012 C conf
MVC real-time video encoder for full-HDTV 3D video.
ICCE
Mitsuo Ikeda, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Hiroe Iwasaki, Yasuyuki Nakajima, Koyo Nitta, Yasuko Takahashi, Kazuya Yokohari, Daisuke Kobayashi, Kazuto Kamikura, Hirohisa Jozawa
2008 C conf
Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI.
ISCAS
Takayuki Onishi, Takashi Sano, Koyo Nitta, Mitsuo Ikeda, Jiro Naganuma
2007 J jnl
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level.
IEEE Trans. Very Large Scale Integr. Syst.
Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima
2003 A conf
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level.
DATE
Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo
1999 J jnl
A 4: 2: 2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI.
IEEE Trans. Consumer Electron.
Takeshi Yoshitome, Toshihiro Minami, Mitsuo Ikeda, Koyo Nitta, Kazuhito Suguri
1999 A conf
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture.
DATE
Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura
1999 J jnl
SuperENC: MPEG-2 video encoder chip.
IEEE Micro
Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe, Naoki Kobayashi, Tsuneo Okubo, Ryota Kasai