Koushik K. Das

11 papers A 3B 1Misc 2Journal 3Unranked 2
YearRankTypeTitle / Venue / Authors
2016 B conf
Security, Compliance, and Agile Deployment of Personal Identifiable Information Solutions on a Public Cloud.
CLOUD
Yasuharu Katsuno, Ashish Kundu, Koushik K. Das, Hitomi Takahashi, Robert Schloss, Prasenjit Dey, Mukesh K. Mohania
2009 A conf
Yield estimation of SRAM circuits using "Virtual SRAM Fab".
ICCAD
Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das
2008 J jnl
Reducing parasitic BJT effects in partially depleted SOI digital logic circuits.
Microelectron. J.
Koushik K. Das, Ching-Te Chuang, Richard B. Brown
2007 J jnl
An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability.
Proc. IEEE
Koushik K. Das, Steven G. Walker, Manjul Bhushan
2006 Misc conf
High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.
VLSI Design
Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang
2006 J jnl
Ultralow-voltage, minimum-energy CMOS.
IBM J. Res. Dev.
Scott Hanson, Bo Zhai, Kerry Bernstein, David T. Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester
2004 A conf
Nanoscale CMOS circuit leakage power reduction by double-gate device.
ISLPED
Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang
2003 — conf
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology.
ESSCIRC
Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
2003 A conf
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology.
ISLPED
Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
2003 — conf
Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS.
ISVLSI
Koushik K. Das, Richard B. Brown
2003 Misc conf
Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology.
VLSI Design
Koushik K. Das, Richard B. Brown