Kouichi Kanda

25 papers A 1B 1C 1Journal 12Unranked 10
YearRankTypeTitle / Venue / Authors
2025 J jnl
MOCQA: A Multi-Core Optimizer for Constrained Quadratic Assignment.
IEEE Access
Mohammad Bagherbeik, Parastoo Ashtari, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2024 C conf
Digital Annealing Engine for High-speed Solving of Constrained Binary Quadratic Problems on Multiple GPUs.
ICCE
Kentaro Katayama, Noboru Yoneoka, Kouichi Kanda, Hirotaka Tamura, Hiroshi Nakayama, Yasuhiro Watanabe
2022 A conf
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA.
FPGA
Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2022 — conf
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization.
VLSI Technology and Circuits
Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2020 — conf
A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems.
PPSN (1)
Mohammad Bagherbeik, Parastoo Ashtari, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami
2015 J jnl
A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications.
IEEE J. Biomed. Health Informatics
Ao Ba, Maja Vidojkovic, Kouichi Kanda, Nauman F. Kiyani, Maarten Lont, Xiongchuan Huang, Xiaoyan Wang, Cui Zhou, Yao-Hong Liu, Ming Ding, Benjamin Busze, Shoichi Masui, Makoto Hamaminato, Hiroyuki Sato, Kathleen Philips, Harmke de Groot
2015 — conf
A 3.5mW 315/400MHz IEEE802.15.6/proprietary mode digitally-tunable radio SoC with integrated digital baseband and MAC processor in 40nm CMOS.
VLSIC
Christian Bachmann, Maja Vidojkovic, Xiongchuan Huang, Maarten Lont, Yao-Hong Liu, Ming Ding, Benjamin Busze, Jordy Gloudemans, Hans Giesen, Adnane Sbai, Gert-Jan van Schaik, Nauman F. Kiyani, Kouichi Kanda, Kazuaki Oishi, Shoichi Masui, Kathleen Philips, Harmke de Groot
2014 — conf
9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications.
ISSCC
Maja Vidojkovic, Xiongchuan Huang, Xiaoyan Wang, Cui Zhou, Ao Ba, Maarten Lont, Yao-Hong Liu, Pieter Harpe, Ming Ding, Ben Busze, Nauman F. Kiyani, Kouichi Kanda, Shoichi Masui, Kathleen Philips, Harmke de Groot
2014 B conf
Radio channel characterization for 400 MHz implanted devices.
WCNC
Hans W. Pflug, Hubregt J. Visser, Nauman F. Kiyani, Guido Dolmans, Kathleen Philips, Kouichi Kanda, Makoto Hamaminato, Shoichi Masui
2012 — conf
A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets.
ISSCC
Kouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura
2011 J jnl
A 60-GHz Injection-Locked Frequency Divider Using Multi-Order
IEICE Trans. Electron.
Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda
2010 J jnl
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
IEEE J. Solid State Circuits
Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker
2010 — conf
A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.
CICC
Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda
2009 J jnl
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.
IEEE J. Solid State Circuits
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2009 — conf
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.
ISSCC
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2008 J jnl
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range.
IEEE J. Solid State Circuits
Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
2007 J jnl
18-GHz Clock Distribution Using a Coupled VCO Array.
IEICE Trans. Electron.
Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
2007 — conf
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.
ISSCC
Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone
2006 J jnl
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.
IEICE Trans. Electron.
Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa
2006 J jnl
Managing subthreshold leakage in charge-based analog circuits with low-V
IEEE J. Solid State Circuits
Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai
2005 J jnl
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-
IEICE Trans. Electron.
Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai
2005 — conf
Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS).
ISCAS (4)
Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai
2004 J jnl
90% write power-saving SRAM using sense-amplifying memory cell.
IEEE J. Solid State Circuits
Kouichi Kanda, Hattori Sadaaki, Takayasu Sakurai
2001 J jnl
Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs.
IEEE J. Solid State Circuits
Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai
1999 — conf
Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs.
CICC
Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai