Kotaro Shimamura

14 papers A 1C 2Journal 7Unranked 4
YearRankTypeTitle / Venue / Authors
2025 — conf
Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-Scalar Multiplication.
COOL CHIPS
Ayumi Ohno, Kotaro Shimamura, Shinya Takamaeda-Yamazaki
2025 J jnl
Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-scalar Multiplication.
CoRR
Ayumi Ohno, Kotaro Shimamura, Shinya Takamaeda-Yamazaki
2025 — conf
Exploring the Versal AI Engine for 3D Gaussian Splatting.
COOL CHIPS
Kotaro Shimamura, Ayumi Ohno, Shinya Takamaeda-Yamazaki
2025 J jnl
Exploring the Versal AI Engine for 3D Gaussian Splatting.
CoRR
Kotaro Shimamura, Ayumi Ohno, Shinya Takamaeda-Yamazaki
2024 — conf
FS-Boost: Communication-Efficient Federated Subtree-Based Gradient Boosting Decision Trees.
CCNC
Kotaro Shimamura, Shinya Takamaeda-Yamazaki
2023 J jnl
Measurement Results of Real Circuit Delay Degradation under Realistic Workload.
IPSJ Trans. Syst. LSI Des. Methodol.
Kotaro Shimamura, Takeshi Takehara, Naohiro Ikeda
2020 J jnl
Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Yusuke Kanno, Tadanobu Toba, Kotaro Shimamura, Nobuyasu Kanekawa
2020 J jnl
Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator.
IPSJ Trans. Syst. LSI Des. Methodol.
Kotaro Shimamura, Naohiro Ikeda
2012 A conf
DART: Dependable VLSI test architecture and its implementation.
ITC
Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
2006 C conf
A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature.
PRDC
Kotaro Shimamura, Takeshi Takehara, Yosuke Shima, Kunihiko Tsunedomi
1998 — conf
A Triple Redundant Controller which Adopts the Time-Sharing Fault Recovery Method and its Application to a Power Converter Controller.
IEEE Real Time Technology and Applications Symposium
Kotaro Shimamura, Yuichiro Morita, Yoshitaka Takahashi, Takashi Hotta, Shigeta Ueda, Mikiya Nohara, Mitsuyasu Kido, Seji Tanaka, Kazuhiro Imaie, Koji Sakamoto, Tatsuhito Nakajima
1996 J jnl
2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor.
IEEE J. Solid State Circuits
Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto
1995 C conf
A superscalar RISC processor with pseudo vector processing feature.
ICCD
Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa
1994 J jnl
A 120-MHz BiCMOS superscalar RISC processor.
IEEE J. Solid State Circuits
Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura