Kota Ando

35 papers A* 1B 3C 1Journal 12Unranked 18
YearRankTypeTitle / Venue / Authors
2025 J jnl
Amorphica: A Fully Connected Annealer Supporting Metamorphic Annealing and Scalable Multi Chip Integration.
IEEE Access
Daiki Okonogi, Jaehoon Yu, Satoru Jimbo, Genta Inoue, Akira Hyodo, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2025 — conf
Co-Optimization of Models and Hardware for Neural Network Inference in Variable-Parallelism Processor.
CANDARW
Yu Inoue, Atsushi Hori, Takao Marukame, Tetsuya Asai, Alexandre Schmid, Kota Ando
2024 — conf
A Stacked FPGA utilizing 3D-SRAM with Latency Optimization.
MCSoC
Ryo Takahashi, Kota Ando, Hiroki Nakahara
2024 B conf
Edge AI Online Training Architecture Using Multi-Phase-Quantization Optimizer.
IJCNN
Itsuki Akeno, Hiiro Yamazaki, Tetsuya Asai, Kota Ando
2024 J jnl
Extending Binary Neural Networks to Bayesian Neural Networks with Probabilistic Interpretation of Binary Weights.
IEICE Trans. Inf. Syst.
Taisei Saito, Kota Ando, Tetsuya Asai
2024 B conf
Out-of-distribution Data Detection using Bayesian Convolutional Neural Network with Variational Inference.
IJCNN
Koki Minagawa, Taisei Saito, Sena Kojima, Kota Ando, Tetsuya Asai
2024 J jnl
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.
IEEE Access
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024 J jnl
SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA.
Int. J. Parallel Emergent Distributed Syst.
Yuki Abe, Kohei Nishida, Kota Ando, Tetsuya Asai
2023 J jnl
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems.
IEICE Trans. Inf. Syst.
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2023 — conf
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension.
ISSCC
Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
2023 — conf
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.
VLSI Technology and Circuits
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2023 J jnl
TT-MLP: Tensor Train Decomposition on Deep MLPs.
IEEE Access
Jiale Yan, Kota Ando, Jaehoon Yu, Masato Motomura
2022 J jnl
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers.
IEICE Trans. Inf. Syst.
Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2022 — conf
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control.
IPDPS Workshops
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2022 — conf
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet.
ISSCC
Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
2022 A* conf
Multicoated Supermasks Enhance Hidden Networks.
ICML
Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2021 — conf
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner.
HCS
Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2021 J jnl
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation.
Int. J. Netw. Comput.
Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2021 J jnl
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions.
IEEE J. Solid State Circuits
Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2020 — conf
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions.
ISSCC
Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2020 C conf
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes.
ISCAS
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
2020 — conf
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation.
CANDAR
Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2019 — conf
DeltaNet: Differential Binary Neural Network.
ASAP
Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2019 J jnl
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks.
IEICE Trans. Inf. Syst.
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2019 J jnl
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.
IEEE J. Solid State Circuits
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
2018 — conf
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators.
MCSoC
Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2018 J jnl
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.
IEEE J. Solid State Circuits
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
2018 — conf
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware.
FPT
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2018 — conf
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS.
ISSCC
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
2017 — conf
Accelerating deep learning by binarized hardware.
APSIPA
Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017 B conf
Exploring optimized accelerator design for binarized convolutional neural networks.
IJCNN
Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017 — conf
In-memory area-efficient signal streaming processor design for binary neural networks.
MWSCAS
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017 — conf
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training.
CANDAR
Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2017 — conf
Quantization Error-Based Regularization in Neural Networks.
SGAI Conf.
Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2016 — conf
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting.
ReConFig
Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura