Kostas Adaos

11 papers C 5Journal 2Unranked 4
YearRankTypeTitle / Venue / Authors
2014 — conf
Automated Generation of the Register Set of a SOC and its Verification Environment.
Panhellenic Conference on Informatics
K. Poulos, Kostas Adaos, George Alexiou
2011 — conf
Digital baseband challenges for a 60GHz gigabit link.
ICECS
Nikos Kanistras, Ioannis Tsatsaragkos, Ahmed Mahdi, Konstantina Karagianni, Vassilis Paliouras, Fotios Gioulekas, E. Lalos, Kostas Adaos, Michael K. Birbas, Panos Karaivazoglou, M. V. Koziotis, M. Perakis
2008 C conf
A Novel System-on-Chip Architecture for Efficient Image Processing.
IEEE International Workshop on Rapid System Prototyping
V. Mariatos, Kostas Adaos, George Alexiou
2007 C conf
Design and Implementation of a Reconfigurable, Embedded Real-Time Face Detection System.
IEEE International Workshop on Rapid System Prototyping
V. Mariatos, Kostas Adaos, George Alexiou
2006 J jnl
A core generator for arithmetic cores and testing structures with a network interface.
J. Syst. Archit.
Dimitris Bakalis, Kostas Adaos, Dimitrios Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
2001 C conf
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores.
IEEE International Workshop on Rapid System Prototyping
Dimitris Bakalis, Kostas Adaos, George Alexiou, Dimitris Nikolos, Dimitrios Lymperopoulos
2000 — conf
Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures.
ICECS
Kostas Adaos, George Alexiou, Nick Kanopoulos
1999 C conf
Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping.
IEEE International Workshop on Rapid System Prototyping
A. Vasilliou, Konstantinos Gounaris, Kostas Adaos, D. Mitsainas, George Alexiou, Dimitris Nikolos
1999 — conf
Efficient implementation of a serial/parallel multiplier for IP based development and rapid prototyping in VLSI digital signal processing.
ICECS
Kostas Adaos, G. Ph. Alexiou, Nikos Kanopoulos
1998 C conf
An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs.
International Workshop on Rapid System Prototyping
Kostas Adaos, George Alexiou, Nick Kanopoulos
1995 J jnl
A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier.
Int. J. Circuit Theory Appl.
Theodore Karoubalis, Kostas Adaos, George Alexiou, Nick Kanopoulos