Konrad Möller

15 papers A 1B 2C 2Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2019 A conf
Reconfigurable Convolutional Kernels for Neural Networks on FPGAs.
FPGA
Martin Hardieck, Martin Kumm, Konrad Möller, Peter Zipf
2019 J jnl
World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mario Garrido, Konrad Möller, Martin Kumm
2018 B conf
ILP-Based Modulo Scheduling and Binding for Register Minimization.
FPL
Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch
2018 J jnl
Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Konrad Möller, Martin Kumm, Mario Garrido, Peter Zipf
2017 — conf
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits.
MBMV
Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf
2017 — conf
Model-based hardware design based on compatible sets of isomorphic subgraphs.
FPT
Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis
2017 J jnl
Reconfigurable Constant Multiplication for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf
2017 — —
Run-time Reconfigurable Constant Multiplication on Field Programmable Gate Arrays.
Konrad Möller
2015 J jnl
Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits.
CoRR
Konrad Möller, Martin Kumm, Charles-Frederic Müller, Peter Zipf
2014 — conf
Dynamically Reconfigurable Constant Multiplication on FPGAs.
MBMV
Konrad Möller, Martin Kumm, Björn Barschtipan, Peter Zipf
2014 B conf
Pipelined reconfigurable multiplication with constants on FPGAs.
FPL
Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf
2013 — conf
Dynamically reconfigurable FIR filter architectures with fast reconfiguration.
ReCoSoC
Martin Kumm, Konrad Möller, Peter Zipf
2013 J jnl
FIR filter optimization for video processing on FPGAs.
EURASIP J. Adv. Signal Process.
Martin Kumm, Diana Fanghänel, Konrad Möller, Peter Zipf, Uwe Meyer-Baese
2013 C conf
Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs.
ISCAS
Martin Kumm, Konrad Möller, Peter Zipf
2013 C conf
Reconfigurable FIR filter using distributed arithmetic on FPGAs.
ISCAS
Martin Kumm, Konrad Möller, Peter Zipf