Koji Sakui - RankMe

21 papers C 1Journal 12Unranked 8

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Through Silicon Via (TSV) Architecture of the Bumpless Build Cube (BBCube) for Stacked Memory Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. Shinji Sugatani, Hiroyuki Ryoson, Norio Chujo, Masao Taguchi, Koji Sakui, Takayuki Ohba
2025	J	`jnl`	Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WOW and COW. IEEE J. Emerg. Sel. Topics Circuits Syst. Norio Chujo, Hiroyuki Ryoson, Koji Sakui, Shinji Sugatani, Masao Taguchi, Takayuki Ohba
2025	—	`conf`	Dynamic Flash Memory Operation Experimentally Validated with 65nm SOI Technology. IMW Koji Sakui, Daniele Garbin, Yoshihisa Iwata, Gautam Gaddemane, Yisuo Li, Yiqun Wan, Ken'ichi Kanazawa, Eyup Can Demir, Iwao Kunishima, Andrea Fantini, Masakazu Kakumu, Christophe Lorant, Nozomu Harada
2023	—	`conf`	Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy. VLSI Technology and Circuits Norio Chujo, Koji Sakui, Shinji Sugatani, Hiroyuki Ryoson, Tomoji Nakamura, Takayuki Ohba
2022	—	`conf`	Dynamic Flash Memory with Fast Block Refresh. NVMTS Koji Sakui, Masakazu Kakumu, Nozomu Harada
2021	—	`conf`	1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar. IMW Yisuo Li, Ken'ichi Kanazawa, Tetsuo Izawa, Koji Sakui, Georg Strof, Oskar Baumgartner, Gerhard Rzepa, Markus Karner, Zlatan Stanojevic, Nozomu Harada, Fujio Masuoka
2021	—	`conf`	Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT). IMW Koji Sakui, Nozomu Harada
2021	—	`conf`	Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs. IRPS Zhwen Chen, Young-Suk Kim, Tadashi Fukuda, Koji Sakui, Takayuki Ohba, Tatsuji Kobayashi, Takashi Obara
2019	—	`conf`	High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology. 3DIC Koji Sakui, Takayuki Ohba
2019	—	`conf`	Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform. CICC Koji Sakui, Takayuki Ohba
2010	C	`conf`	A compact and low power logic design for multi-pillar vertical MOSFETs. ISCAS Koji Sakui, Tetsuo Endoh
2010	J	`jnl`	Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure. IEICE Trans. Electron. Tetsuo Endoh, Koji Sakui, Yukio Yasuda
2010	J	`jnl`	Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET. IEICE Trans. Electron. Tetsuo Endoh, Koji Sakui, Yukio Yasuda
2000	J	`jnl`	A source-line programming scheme for low-voltage operation NAND flash memories. IEEE J. Solid State Circuits Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui
1999	J	`jnl`	A 130-mm/ IEEE J. Solid State Circuits Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui
1999	J	`jnl`	A CMOS bandgap reference circuit with sub-1-V operation. IEEE J. Solid State Circuits Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi, Koji Sakui
1999	J	`jnl`	A negative V IEEE J. Solid State Circuits Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui
1997	J	`jnl`	A 120-mm IEEE J. Solid State Circuits Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto
1994	J	`jnl`	A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. IEEE J. Solid State Circuits Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara
1993	J	`jnl`	BiCMOS circuit technology for high-speed DRAMs. IEEE J. Solid State Circuits Shigeyoshi Watanabe, Koji Sakui, Tsuneaki Fuse, Takahiko Hara, Seiichi Aritome, Katsuhiko Hieda
1989	J	`jnl`	An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. IEEE J. Solid State Circuits Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka