Koichiro Takayama

13 papers A* 2A 3C 2Journal 4Unranked 2
YearRankTypeTitle / Venue / Authors
2014 A conf
Software Defect Prediction for LSI Designs.
ICSME
Matthieu Parizy, Koichiro Takayama, Yuji Kanazawa
2004 — conf
High level hardware validation using hierarchical message sequence charts.
HLDVT
Praveen K. Murthy, Sreeranga P. Rajan, Koichiro Takayama
2002 A* conf
Effective safety property checking using simulation-based sequential ATPG.
DAC
Shuo Sheng, Koichiro Takayama, Michael S. Hsiao
2002 J jnl
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table.
Formal Methods Syst. Des.
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita
2001 C conf
A New Functional Test Program Generation Methodology.
ICCD
Farzan Fallah, Koichiro Takayama
2001 J jnl
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama
2000 — conf
Automatic partitioning for efficient combinatorial verification.
ASP-DAC
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita
1999 A conf
An Efficient Filter-Based Approach for Combinational Verification.
DATE
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1999 J jnl
An efficient filter-based approach for combinational verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1999 A* conf
Model Checking Based on Sequential ATPG.
CAV
Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita
1998 C conf
An approach to verify a large scale system-on-a-chip using symbolic model checking.
ICCD
Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose
1990 J jnl
A high-speed test-generation method using a test generation circuit.
Syst. Comput. Jpn.
Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato
1988 A conf
A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator.
ITC
Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato