Koichiro Mashiko

24 papers A 2C 1Journal 20Unranked 1

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	Evaluation of SRAM PUF Characteristics and Generation of Stable Bits for IoT Security. IRICT Pyi Phyo Aung, Koichiro Mashiko, Nordinah Binti Ismail, Chia Yee Ooi
2007	J	`jnl`	A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. IEICE Trans. Electron. Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada
2006	J	`jnl`	Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada
2006	J	`jnl`	High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masafumi Uemori, Haruo Kobayashi, Tomonari Ichikawa, Atsushi Wada, Koichiro Mashiko, Toshiro Tsukada, Masao Hotta
2000	J	`jnl`	A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara
1997	C	`conf`	A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. ICCD Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano
1997	J	`jnl`	Authors Reply. IEEE J. Solid State Circuits Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko
1997	J	`jnl`	Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
1996	J	`jnl`	A 1.9-GHz single chip IF transceiver for digital cordless phones. IEEE J. Solid State Circuits Hisayasu Sato, Kenichi Kashiwagi, Kazuhito Niwano, Tetsuya Iga, Tatsuhiko Ikeda, Koichiro Mashiko, Tadashi Sumi, Koji Tsuchihashi
1996	J	`jnl`	A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
1996	J	`jnl`	A 64-bit carry look ahead adder using pass transistor BiCMOS gates. IEEE J. Solid State Circuits Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko
1996	J	`jnl`	A fully compensated active pull-down ECL circuit with self-adjusting driving capability. IEEE J. Solid State Circuits Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Koichiro Mashiko
1996	J	`jnl`	An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko
1996	A	`conf`	How to design low-power digital cellular phones. ISLPED Koichiro Mashiko
1996	J	`jnl`	Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
1995	J	`jnl`	A BiCMOS wired-OR logic. IEEE J. Solid State Circuits Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko
1994	J	`jnl`	A voltage compensated series-gate bipolar circuit operating at sub-2 V. IEEE J. Solid State Circuits Hisayasu Sato, Kimio Ueda, Nagisa Sasaki, Tatsuhiko Ikeda, Koichiro Mashiko
1991	J	`jnl`	A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing. IEEE J. Solid State Circuits Yasunobu Nakase, Kakutaro Suda, Koichiro Mashiko, Tatsuhiko Ikeda, Shinpei Kayano
1991	J	`jnl`	A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture. IEEE J. Solid State Circuits Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Hiromi Notani, Harufusa Kondoh, Shinpei Kayano
1991	J	`jnl`	A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates. IEEE J. Solid State Circuits Toshiaki Hanibuchi, Masahiro Ueda, Keiichi Higashitani, Masahiro Hatanaka, Koichiro Mashiko, Akiharu Tada
1991	J	`jnl`	A self-learning neural network chip with 125 neurons and 10 K self-organization synapses. IEEE J. Solid State Circuits Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Harufusa Kondoh, Shimpei Kayano
1990	J	`jnl`	A speed-enhanced DRAM array architecture with embedded ECC. IEEE J. Solid State Circuits Kazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Masaki Tsukude, Tsukasa Ooishi, Koichiro Mashiko, Kuzuyasu Fujishima
1989	J	`jnl`	A built-in Hamming code ECC circuit for DRAMs. IEEE J. Solid State Circuits Kiyohiro Furutani, Kazutami Arimoto, Hiroshi Miyamoto, Toshifumi Kobayashi, Kenichi Yasuda, Koichiro Mashiko
1985	A	`conf`	Test Pattern Considerations for Fault Tolerant High Density DRAM. ITC Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, Takao Nakano