Koichiro Ishibashi

75 papers A 2B 1C 2Journal 39Unranked 30

Year	Rank	Type	Title / Venue / Authors
2023	C	`conf`	Energy Saving LED Lighting System using Illumination Beat Sensors. ICCE Koichiro Ishibashi, Yuki Ogawa
2022	—	`conf`	Deep Learning Approach for Classifying Bacteria types using Morphology of Bacterial Colony. EMBC Masaki Amano, Duc-Tho Mai, Guanghao Sun, Trung Nguyen Vu, Le Thi Hoi, Nguyen Thi Hoa, Koichiro Ishibashi
2022	—	`conf`	High-Accuracy and Long-Range Energy Harvesting Beat Sensor with LoRa. IEEE SENSORS Tuan-Anh Tran, Koichiro Ishibashi
2022	—	`conf`	Keynote Talk #1 RF Energy Harvesting Technology and IoT Applications. RIVF Koichiro Ishibashi
2022	J	`jnl`	Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs Marco Sarmiento, Khai-Duy Nguyen, Ckristian Duran, Ronaldo Serrano, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham
2021	—	`conf`	A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. ISOCC Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham
2021	J	`jnl`	A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs Marco Sarmiento, Khai-Duy Nguyen, Ckristian Duran, Trong-Thuc Hoang, Ronaldo Serrano, Van-Phuc Hoang, Xuan-Tu Tran, Koichiro Ishibashi, Cong-Kha Pham
2021	—	`conf`	Bacteria Shape Classification using Small-Scale Depthwise Separable CNNs. EMBC Duc-Tho Mai, Koichiro Ishibashi
2021	J	`jnl`	High Accuracy Heartbeat Detection from CW-Doppler Radar Using Singular Value Decomposition and Matched Filter. Sensors Yuki Iwata, Han Trong Thanh, Guanghao Sun, Koichiro Ishibashi
2021	J	`jnl`	Short time cardio-vascular pulses estimation for dengue fever screening via continuous-wave Doppler radar using empirical mode decomposition and continuous wavelet transform. Biomed. Signal Process. Control. Nguyen Dinh Chinh, Ha Manh Luu, Guanghao Sun, Le Quoc Anh, Pham Viet Huong, Tran Anh Vu, Tran Trong Hieu, Duc-Tan Tran, Trung Nguyen Vu, Koichiro Ishibashi, Nguyen Linh Trung
2020	—	`conf`	Contactless Heartbeat Detection from CW-Doppler Radar using Windowed-Singular Spectrum Analysis EMBC Yuki Iwata, Koichiro Ishibashi, Guanghao Sun, Ha Manh Luu, Trong Thanh Han, Nguyen Linh Trung, Do Trong Tuan
2019	B	`conf`	Dengue Fever Screening Using Vital Signs by Contactless Microwave Radar and Machine Learning. SAS Xiaofeng Yang, Koki Kumagai, Guanghao Sun, Koichiro Ishibashi, Le Thi Hoi, Trung Nguyen Vu, Kinh Nguyen Van
2019	—	`conf`	Long Battery Life IoT Sensing by Beat Sensors. ICPS Koichiro Ishibashi, Ryohei Takitoge, Duangchak Manyvone, Nobuto Ono, Shigeya Yamaguchi
2019	—	`conf`	Non-Contact Blood Pressure Measurement Scheme Using Doppler Radar. EMBC Tomoyuki Ohata, Koichiro Ishibashi, Guanghao Sun
2019	—	`conf`	Precise Heart Rate Measurement Using Non-contact Doppler Radar Assisted by Machine-Learning-Based Sleep Posture Estimation. EMBC Kotaro Higashi, Guanghao Sun, Koichiro Ishibashi
2018	—	`ed.`	2018 International Conference on Advanced Computing and Applications, ACOMP 2018, Ho Chi Minh City, Vietnam, November 27-29, 2018 ACOMP Lam-Son Lê, Tran Khanh Dang, Koichiro Ishibashi, Tran Ngoc Thinh, Cuong Pham-Quoc, Quang Tran Minh
2018	J	`jnl`	83nJ/bit Transmitter Using Code-Modulated Synchronized-OOK on 65nm SOTB for Normally-Off Wireless Sensor Networks. IEICE Trans. Electron. Van-Trung Nguyen, Ryo Ishikawa, Koichiro Ishibashi
2018	—	`conf`	A 375 nA Input Off Current Schmitt Triger LDO for Energy Harvesting IoT Sensors. ISVLSI Koichiro Ishibashi, Shiho Takahashi
2018	—	`conf`	Dengue Fever Detecting System Using Peak-detection of Data from Contactless Doppler Radar. EMBC Xiaofeng Yang, Koichiro Ishibashi, Le Hoi, Trung Nguyen Vu, Kinh Nguyen Van, Guanghao Sun
2018	—	`conf`	Energy-aware receiver-driven medium access control protocol for wireless energy-harvesting sensor networks. CCNC Ryo Tanabe, Tatsuhiro Kawaguchi, Ryohei Takitoge, Koichiro Ishibashi, Koji Ishibashi
2018	—	`conf`	Implementation of condition-aware receiver-initiated MAC protocol to realize energy-harvesting wireless sensor networks. CCNC Tatsuhiro Kawaguchi, Ryo Tanabe, Ryohei Takitouge, Koichiro Ishibashi, Koji Ishibashi
2018	—	`conf`	Plants Growth Sensing Using Beat Sensors. IEEE SENSORS Koichiro Ishibashi, Yuu Oota, Kosuke Suzuki, Ryohei Takitoge
2017	—	`conf`	A 910nW delta sigma modulator using 65nm SOTB technology for mixed signal IC of IoT applications. ICICDT Koichiro Ishibashi, Junya Kikuchi, Nobuyuki Sugii
2017	—	`conf`	Low-power enhanced temperature beat sensor with longer communication distance by data-recovery algorithm. IEEE SENSORS Ryohei Takitoge, Masataka Kishi, Koichiro Ishibashi
2017	—	`conf`	Non-contact acquisition of respiration and heart rates using Doppler radar with time domain peak-detection algorithm. EMBC Xiaofeng Yang, Guanghao Sun, Koichiro Ishibashi
2017	—	`conf`	Short Time and Contactless Virus Infection Screening System with Discriminate Function Using Doppler Radar. BIC-TA Xiaofeng Yang, Koichiro Ishibashi, Toshiaki Negishi, Tetsuo Kirimoto, Guanghao Sun
2016	—	`conf`	Temperature beat: Persistent and energy harvesting wireless temperature sensing scheme. IEEE SENSORS Ryohei Takitoge, Shohei Ishigaki, Tsuyoshi Ishige, Koichiro Ishibashi
2015	J	`jnl`	A 27.6 µW 315 MHz low-complexity OOK receiver with on-off RF front-end. IEICE Electron. Express Minh-Thien Hoang, Nobuyuki Sugii, Koichiro Ishibashi
2015	J	`jnl`	A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
2015	—	`conf`	Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process. ICICDT Duc-Hung Le, Nobuyuki Sugii, Shiro Kamohara, Xuan-Thuan Nguyen, Koichiro Ishibashi, Cong-Kha Pham
2014	—	`conf`	A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa
2014	—	`conf`	A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
2013	J	`jnl`	On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. IEICE Trans. Electron. Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2012	—	`conf`	An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. SoCC Kazuo Otsuga, Masafumi Onouchi, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa
2012	J	`jnl`	On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Trans. Electron. Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process. A-SSCC Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa
2011	C	`conf`	Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011	J	`jnl`	On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Trans. Electron. Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2011	—	`conf`	On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada
2010	J	`jnl`	A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. IEEE J. Solid State Circuits Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi
2008	J	`jnl`	A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	J	`jnl`	A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	—	`conf`	A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. ISSCC Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	J	`jnl`	Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias. IEICE Trans. Electron. Yoshihide Komatsu, Koichiro Ishibashi, Makoto Nagata
2006	J	`jnl`	Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. IEICE Trans. Electron. Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada
2006	J	`jnl`	Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond. IEICE Trans. Electron. Yoshihide Komatsu, Yukio Arima, Koichiro Ishibashi
2005	J	`jnl`	An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs. IEEE J. Solid State Circuits Toshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, Koichiro Ishibashi
2005	J	`jnl`	Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. Syst. Comput. Jpn. Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai
2005	J	`jnl`	Power Valve: for low power operation and low stand-by power. IEICE Electron. Express Takahiro Yamashita, Tetsuya Fujimoto, Koichiro Ishibashi
2005	J	`jnl`	Special Section on Low-Power LSI and Low-Power IP. IEICE Trans. Electron. Koichiro Ishibashi
2005	—	`conf`	Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. CICC Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata
2005	A	`conf`	Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2004	J	`jnl`	0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. IEEE J. Solid State Circuits Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi
2004	—	`conf`	A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond. CICC Yoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi
2003	J	`jnl`	16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors. IEEE J. Solid State Circuits Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi
2003	—	`conf`	Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technology. ESSCIRC Hiroyuki Okada, Yasuyuki Hashimoto, Kohji Sakata, Toshiro Tsukada, Koichiro Ishibashi
2002	J	`jnl`	A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias. IEEE J. Solid State Circuits Masayuki Miyazaki, Goichi Ono, Koichiro Ishibashi
2002	J	`jnl`	A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit. IEEE J. Solid State Circuits Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi
2001	—	`conf`	CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip. CICC Shoji Shukuri, Kazumasa Yanagisawa, Koichiro Ishibashi
2001	J	`jnl`	Universal-V IEEE J. Solid State Circuits Kenichi Osada, Jinuk Luke Shin, Masood Khan, Yude Liou, Karl Wang, Kenichi Shoji, Kenichi Kuroda, Shuji Ikeda, Koichiro Ishibashi
1999	J	`jnl`	A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. IEEE Trans. Very Large Scale Integr. Syst. Hiroyuki Mizuno, Koichiro Ishibashi
1999	J	`jnl`	An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. IEEE J. Solid State Circuits Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, Kunio Uchiyama
1998	A	`conf`	A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. ISLPED Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi
1996	J	`jnl`	A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. IEEE J. Solid State Circuits Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure
1995	J	`jnl`	A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. IEEE J. Solid State Circuits Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida
1995	J	`jnl`	A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. IEEE J. Solid State Circuits Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida
1994	J	`jnl`	A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. IEEE J. Solid State Circuits Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki
1993	J	`jnl`	A 16-Mb CMOS SRAM with a 2.3- mu m IEEE J. Solid State Circuits Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nagatoshi Ohki
1992	J	`jnl`	A 1-V TFT-load SRAM using a two-step word-voltage method. IEEE J. Solid State Circuits Koichiro Ishibashi, Koichi Takasugi, Toshiaki Yamanaka, Takashi Hashimoto, Katsuro Sasaki
1992	J	`jnl`	A 1.7-V adjustable I/O interface for low-voltage fast SRAMs. IEEE J. Solid State Circuits Koichiro Ishibashi, Katsuro Sasaki, Toshiaki Yamanaka, Hiroshi Toyoshima, Fumio Kojima
1992	J	`jnl`	A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier. IEEE J. Solid State Circuits Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, Akihiro Shimizu
1992	J	`jnl`	A voltage down converter with submicroampere standby current for low-power static RAMs. IEEE J. Solid State Circuits Koichiro Ishibashi, Katsuro Sasaki, Hiroshi Toyoshima
1990	J	`jnl`	A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current. IEEE J. Solid State Circuits Katsuro Sasaki, Koichiro Ishibashi, Katsuhiro Shimohigashi, Toshiaki Yamanaka, Nobuyuki Moriwake, Shigeru Honjo, Shuji Ikeda, Atsuyoshi Koike, Satoshi Meguro, Osamu Minato
1990	J	`jnl`	An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell. IEEE J. Solid State Circuits Koichiro Ishibashi, Toshiaki Yamanaka, Katsuhiro Shimohigashi
1989	J	`jnl`	A 9-ns 1-Mbit CMOS SRAM. IEEE J. Solid State Circuits Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo