Koichi Nose - RankMe

27 papers A 3Journal 9Unranked 15

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications. ISSCC Koichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami, Daichi Hayashi, Teruhito Tanaka, Takao Toi
2019	—	`conf`	A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm VLSI Circuits Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose
2015	—	`conf`	F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels. ISSCC Marian Verhelst, Dennis Sylvester, Makoto Takamiya, Mike Clinton, Kathy Wilcox, Koichi Nose
2015	—	`conf`	Session 16 overview: Emerging technologies enabling next-generation systems: Technology directions subcommittee. ISSCC Jan Genoe, Koichi Nose
2012	J	`jnl`	A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. IEEE J. Solid State Circuits Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno
2012	—	`conf`	A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme. VLSIC Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno
2010	—	`conf`	A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. ISSCC Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno
2010	J	`jnl`	An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. IEEE J. Solid State Circuits Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda
2009	J	`jnl`	On-Chip Optical Interconnect. Proc. IEEE Keishi Ohashi, Kenichi Nishi, Takanori Shimizu, Masafumi Nakada, Junichi Fujikata, Jun Ushida, Sunao Torii, Koichi Nose, Masayuki Mizuno, Hiroaki Yukawa, Masao Kinoshita, Nobuo Suzuki, Akiko Gomyo, Tsutomu Ishi, Daisuke Okamoto, Katsuya Furue, Toshihide Ueno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Jun Akedo
2009	—	`conf`	Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno
2008	J	`jnl`	A 0.016 mm IEEE J. Solid State Circuits Koichi Nose, Masayuki Mizuno
2008	J	`jnl`	LSI On-Chip Optical Interconnection with Si Nano-Photonics. IEICE Trans. Electron. Junichi Fujikata, Kenichi Nishi, Akiko Gomyo, Jun Ushida, Tsutomu Ishi, Hiroaki Yukawa, Daisuke Okamoto, Masafumi Nakada, Takanori Shimizu, Masao Kinoshita, Koichi Nose, Masayuki Mizuno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Keishi Ohashi
2007	—	`conf`	Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. ISSCC Toru Nakura, Koichi Nose, Masayuki Mizuno
2007	—	`conf`	LAGS System Using Data/Instruction Grain Power Control. ISSCC Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada
2006	J	`jnl`	A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. IEEE J. Solid State Circuits Koichi Nose, Mikihiro Kajita, Masayuki Mizuno
2006	—	`conf`	A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. ISSCC Koichi Nose, Mikihiro Kajita, Masayuki Mizuno
2006	—	`conf`	Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics. ISSCC Keishi Ohashi, Junichi Fujikata, Masafumi Nakada, Tsutomu Ishi, Kenichi Nishi, Hirohito Yamada, Muneo Fukaishi, Masayuki Mizuno, Koichi Nose, Ichiro Ogura, Yutaka Urino, Toshio Baba
2004	—	`conf`	Frequency-hopping vernier clock generators for multiple clock domain SoCs. CICC Hiroshi Kodama, Masayuki Mizuno, Koichi Nose, Akio Tanaka
2002	A	`conf`	Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. ISLPED Koichi Nose, Takayasu Sakurai
2002	J	`jnl`	V IEEE J. Solid State Circuits Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai
2001	A	`conf`	Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. ISLPED Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai
2001	—	`conf`	V CICC Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai
2000	J	`jnl`	A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current. IEEE J. Solid State Circuits Hiroshi Kawaguchi, Koichi Nose, Takayasu Sakurai
2000	J	`jnl`	Analysis and future trend of short-circuit power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Koichi Nose, Takayasu Sakurai
2000	—	`conf`	Optimization of VDD and VTH for low-power and high speed applications. ASP-DAC Koichi Nose, Takayasu Sakurai
2000	A	`conf`	Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED Koichi Nose, Soo-Ik Chae, Takayasu Sakurai
1998	—	`conf`	Integrated Current Sensing Device for Micro IDDQ Test. Asian Test Symposium Koichi Nose, Takayasu Sakurai