Kohei Onizuka

28 papers B 1Journal 9Unranked 18
YearRankTypeTitle / Venue / Authors
2023 J jnl
An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs.
IEEE J. Solid State Circuits
Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka
2021 — conf
A 5.7GHz RF Wireless Power Transfer Receiver Using 84.5% Efficiency 12V SIDO Buck-Boost DC-DC Converter with Internal Power Supply Mode.
A-SSCC
Tomohiro Higuchi, Dai Suzuki, Ryo Ishida, Yasuaki Isshiki, Kazuki Arai, Kohei Onizuka, Kousuke Miyaji
2021 — conf
A Tile-based 8×8 Triangular Grid Array Beamformer for 5.7 GHz Microwave Power Transmission.
RWS
Kazuki Arai, Kaili Wang, Toshiya Mitomo, Makoto Higaki, Kohei Onizuka
2020 — conf
18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics.
ISSCC
Satoshi Takaya, Hiroaki Ishihara, Kohei Onizuka
2020 — conf
18.8 A Fully-Generic-Process Galvanic Isolator for Gate Driver with 123mW 23% Power Transfer and Full-Triplex 21/14/0.5Mb/s Bidirectional Communication Utilizing Reference-Free Dual-Modulation FSK.
ISSCC
Hiroaki Ishihara, Kohei Onizuka
2019 — conf
A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs.
ISSCC
Shusuke Kawai, Takeshi Ueno, Kohei Onizuka
2019 J jnl
An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators.
IEEE J. Solid State Circuits
Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Shigeru Maya, Akihide Sai, Kohei Onizuka
2018 — conf
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications.
A-SSCC
Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka
2018 J jnl
An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer.
IEEE J. Solid State Circuits
Shusuke Kawai, Rui Ito, Kengo Nakata, Yutaka Shimizu, Motoki Nagata, Tomohiko Takeuchi, Hiroyuki Kobayashi, Katsuyuki Ikeuchi, Takayuki Kato, Yosuke Hagiwara, Yuki Fujimura, Kentaro Yoshioka, Shigehito Saigusa, Hiroshi Yoshida, Makoto Arai, Toshiyuki Yamagishi, Hirotsugu Kajihara, Kazuhisa Horiuchi, Hideki Yamada, Tomoya Suzuki, Yuki Ando, Kensuke Nakanishi, Koichiro Ban, Masahiro Sekiya, Yoshimasa Egashira, Tsuguhide Aoki, Kohei Onizuka, Toshiya Mitomo
2018 — conf
An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer.
ISSCC
Shusuke Kawai, Hiromitsu Aoyama, Rui Ito, Yutaka Shimizu, Mitsuyuki Ashida, Asuka Maki, Tomohiko Takeuchi, Hiroyuki Kobayashi, Go Urakawa, Hiroaki Hoshino, Shigehito Saigusa, Kazushi Koyama, Makoto Morita, Ryuichi Nihei, Daisuke Goto, Motoki Nagata, Kengo Nakata, Katsuyuki Ikeuchi, Kentaro Yoshioka, Ryoichi Tachibana, Makoto Arai, Chen Kong Teh, Atsushi Suzuki, Hiroshi Yoshida, Yosuke Hagiwara, Takayuki Kato, Ichiro Seto, Tomoya Horiguchi, Koichiro Ban, Kyosuke Takahashi, Hirotsugu Kajihara, Toshiyuki Yamagishi, Yuki Fujimura, Kazuhisa Horiuchi, Katsuya Nonin, Kengo Kurose, Hideki Yamada, Kentaro Taniguchi, Masahiro Sekiya, Takeshi Tomizawa, Daisuke Taki, Masaaki Ikuta, Tomoya Suzuki, Yuki Ando, Daisuke Yashima, Takahisa Kaihotsu, Hiroki Mori, Kensuke Nakanishi, Takeshi Kumagaya, Yasuo Unekawa, Tsuguhide Aoki, Kohei Onizuka, Toshiya Mitomo
2018 — conf
PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators.
VLSI Circuits
Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka
2018 J jnl
PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators.
CoRR
Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka
2017 B conf
Efficient energy beamforming for multi-device microwave wireless power transfer under Tx/Rx power constraints.
PIMRC
Kentaro Murata, Kohei Onizuka, Toshiya Mitomo, Makoto Higaki, Kentaro Taniguchi, Ryoko Matsuo, Tsuguhide Aoki
2017 — conf
F2: High-performance frequency generation for wireless and wireline systems.
ISSCC
Jiayoon Ru, Kohei Onizuka, Pavan Kumar Hanumolu, Roberto Nonis, Howard C. Luong, Jan Craninckx
2017 — conf
Session 2 overview: Power amplifiers.
ISSCC
Kohei Onizuka, Abbas Komijani, Piet Wambacq
2015 — conf
Head ballistocardiogram based on wireless multi-location sensors.
EMBC
Kohei Onizuka, Charles G. Sodini
2014 — conf
3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier.
ISSCC
Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka
2014 — conf
A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations.
CICC
Shouhei Kousai, Kohei Onizuka, Song Hu, Hua Wang, Ali Hajimiri
2014 J jnl
Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier.
IEEE J. Solid State Circuits
Shouhei Kousai, Kohei Onizuka, Junji Wadatsumi, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka
2013 — conf
A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications.
ISSCC
Kohei Onizuka, Shigehito Saigusa, Shoji Otaka
2012 — conf
A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique.
VLSIC
Kohei Onizuka, Shigehito Saigusa, Shoji Otaka
2012 J jnl
A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion.
IEEE J. Solid State Circuits
Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka
2012 J jnl
A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier.
IEEE J. Solid State Circuits
Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka
2012 — conf
A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier.
ISSCC
Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka
2011 — conf
A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller.
CICC
Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka
2007 J jnl
Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs.
IEEE J. Solid State Circuits
Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai
2006 J jnl
$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time.
IEEE J. Solid State Circuits
Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai
2006 — conf
Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications.
CICC
Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda, Takayasu Sakurai