Ko-Chi Kuo - RankMe

32 papers C 1Journal 6Unranked 25

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	A 10-bit 300MS/s Time-Interleaved Successive-Approximation Register Analog-to-Digital Converter with a Binary-Scaled Recombination Weighting Capacitor Array and fault-tolerant. ICCE-Taiwan Ko-Chi Kuo, Hung-Yi Chang, Chun-Wei Huang
2024	—	`conf`	A three reference voltage 0.5V 10-bit SAR-ADC using merge split capacitor switching scheme in 40nm CMOS. ICCE-Taiwan Ko-Chi Kuo, Sin-Cong Huang, Chun-Wei Huang
2023	—	`conf`	A 12-bit 1GS/s Digital to Analog Converter with Switching-Minimized Monotonic Coding. ICCE-Taiwan Ko-Chi Kuo, Shih-En Huang, Hong-Yi Liao
2023	—	`conf`	An Area Efficient Analog Front-End for Sensing EEG Signals with MOS Capacitors in 90nm Process. ICCE-Taiwan Ko-Chi Kuo, Chao-Tung Chen, Hong-Yi Liao
2022	—	`conf`	A 12-bit 1 GS/s Current Steering DAC with the Appointed and Thermometer Coding Scheme. APCCAS Ko-Chi Kuo, Ying-Ju Sung
2022	—	`conf`	A 8-bit 300MHz Domino Based Successive Approximation Register ADC. ISOCC Ko-Chi Kuo, Hsiung-Yu Chi
2021	—	`conf`	A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process. ISOCC Ko-Chi Kuo
2021	—	`conf`	A Novel Linear-Logarithmic Active Pixel CMOS Image Sensor with wide dynamic range. MWSCAS Ko-Chi Kuo
2019	—	`conf`	A 10-bit 250 MS/s Binary Search and Two channel SAR ADC by a two-bit per Conversion with Error Tolerance Ability. ISOCC Ko-Chi Kuo
2019	C	`conf`	A Bio-Sensing System-on-Chip and Software for Smart Clothes. ICCE Hsu-Kang Dow, Ing-Jer Huang, Robert Rieger, Ko-Chi Kuo, Lan-Yuen Guo, Shih-Jung Pao
2019	—	`conf`	A High Speed Low Power Pipelined SAR Analog to Digital Converter. ICICDT Ko-Chi Kuo
2019	—	`conf`	Fast Locking Technique by Using a Programmable Operational Transconductor for a Phase Lock Loop Design. ICICDT Ko-Chi Kuo
2016	—	`conf`	The implementation of HomePlug AV system. ICICDT Ko-Chi Kuo
2015	—	`conf`	A wide-range and harmonic-free SAR all-digital delay locked loop. ISCIT Ko-Chi Kuo, Sz-Hsien Li
2015	—	`conf`	Power saving technique for thermometer-code digital-to-analog converters. ISCIT Ko-Chi Kuo, Chih-Wei Wu
2014	J	`jnl`	A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX. Expert Syst. Appl. Ko-Chi Kuo, Chi-Wei Wu
2012	J	`jnl`	A 120-420 MHz delay-locked loop with multi-band voltage-controlled delay unit. Int. J. Circuit Theory Appl. Ko-Chi Kuo, Yi-Hsi Hsu
2012	—	`conf`	High linear transconductor for multiband CMOS receiver. APCCAS Ko-Chi Kuo, Shan-Yu Chen, Shih-Min Tseng
2012	—	`conf`	Low power delay locked loop with all digital controlled SAR delay cell. APCCAS Ko-Chi Kuo, Chung-Yuan Chang, Si-Hsien Li
2012	—	`conf`	Low power design flow with static and statistical timing analysis. ISPACS Ko-Chi Kuo, Hsueh-Ta Ko
2012	—	`conf`	Power line communication chip design with data error detecting/correcting and data encrypting/decrypting ability. ISPACS Ko-Chi Kuo, Hsun-Chia Hsu
2011	J	`jnl`	A 2.4GHz low phase noise frequency synthesizer for WiMAX applications. IEICE Electron. Express Ko-Chi Kuo
2011	J	`jnl`	A Switching Sequence for Linear Gradient Error Compensation in the DAC Design. IEEE Trans. Circuits Syst. II Express Briefs Ko-Chi Kuo, Chi-Wei Wu
2010	—	`conf`	A fully digital modulator/demodulator for Power Line Communication (PLC). APCCAS Ko-Chi Kuo, Jia-Wei Guo, Yu-Hao Ou
2010	J	`jnl`	Low power and high speed multiplier design with row bypassing and parallel architecture. Microelectron. J. Ko-Chi Kuo, Chi-Wen Chou
2010	—	`conf`	Low power level shifter and combined with logic gates. APCCAS Ko-Chi Kuo, Sheng-Quane Chen
2009	J	`jnl`	A low voltage, high linear, and tunable triode transconductor. IEICE Electron. Express Ko-Chi Kuo, Hsing-Hui Wu
2008	—	`conf`	5 GHz phase locked loop with auto band selection. APCCAS Ko-Chi Kuo, Ming-Jing Chen
2006	—	`conf`	A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS Technology. APCCAS Ko-Chi Kuo, Feng-Ji Wu
2006	—	`conf`	A CMOS High-Speed Nine-Stage Programmable Counter. IMECS Ko-Chi Kuo, Feng-Ji Wu
2006	—	`conf`	A Low-Power Multiplier with Bypassing Logic and Operand Decomposition. IMECS Ko-Chi Kuo, Chi-Wen Chou
2006	—	`conf`	Low Power Multiplier with Bypassing and Tree Strucuture. APCCAS Ko-Chi Kuo, Chi-Wen Chou