Klaas Bult

28 papers Journal 17Unranked 11
YearRankTypeTitle / Venue / Authors
2020 J jnl
A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers.
IEEE Trans. Circuits Syst.
Md Shakil Akter, Rohan Sehgal, Klaas Bult
2018 J jnl
A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers.
IEEE J. Solid State Circuits
Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
2018 J jnl
A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier.
IEEE J. Solid State Circuits
Md Shakil Akter, Rohan Sehgal, Frank M. L. van der Goes, Kofi A. A. Makinwa, Klaas Bult
2018 J jnl
A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier.
IEEE J. Solid State Circuits
Md Shakil Akter, Kofi A. A. Makinwa, Klaas Bult
2017 — conf
A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers.
ESSCIRC
Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
2015 — conf
26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.
ISSCC
Jan Mulder, Davide Vecchi, Yi Ke, Stefano Bozzola, Mark Core, Nitz Saputra, Qiongna Zhang, Jeff Riley, Han Yan, Mattia Introini, Sijia Wang, Christopher M. Ward, Jan R. Westra, Jiansong Wan, Klaas Bult
2015 J jnl
A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration.
IEEE J. Solid State Circuits
Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
2015 — conf
A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction.
ESSCIRC
Md Shakil Akter, Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
2014 — conf
11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS.
ISSCC
Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult
2014 — conf
8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS.
ISSCC
Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult
2014 J jnl
A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS.
IEEE J. Solid State Circuits
Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, Klaas Bult
2014 — conf
A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration.
ESSCIRC
Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult
2014 — conf
Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers.
CICC
Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult
2013 J jnl
A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS.
IEEE J. Solid State Circuits
Silvian Spiridon, Johan van der Tang, Han Yan, Hua-Feng Chen, Davide Guermandi, Xiaodong Liu, Erol Arslan, Frank M. L. van der Goes, Klaas Bult
2011 J jnl
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS.
IEEE J. Solid State Circuits
Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult
2011 — conf
An 800MS/s dual-residue pipeline ADC in 40nm CMOS.
ISSCC
Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult
2009 J jnl
A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS.
IEEE J. Solid State Circuits
Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult
2009 — conf
A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS.
ISSCC
Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult
2009 — conf
Embedded analog-to-digital converters.
ESSCIRC
Klaas Bult
2004 J jnl
A 21-mW 8-b 125-MSample/s ADC in 0.09-mm
IEEE J. Solid State Circuits
Jan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan, Rudy J. van de Plassche, Klaas Bult, Frank M. L. van der Goes
1999 J jnl
A single-chip universal digital satellite receiver with 480-MHz IF input.
IEEE J. Solid State Circuits
Alan Y. Kwentus, Patrick Pai, Steven Jaffe, Ray Gomez, Shauhyuarn Sean Tsai, Tom Kwan, Hing T. Hung, Young J. Shin, Vin Hue, Darwin Cheung, Raheel A. Khan, Christopher M. Ward, Mong-Kai Ku, Kenneth Choi, Jim Searle, Klaas Bult, Kelly B. Cameron, Jason Demas, Charles Reames, Henry Samueli
1998 J jnl
A 10-b, 500-MSample/s CMOS DAC in 0.6 mm
IEEE J. Solid State Circuits
Chi-Hung Lin, Klaas Bult
1998 — conf
Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers.
CICC
Mehdi Hatamian, Oscar E. Agazzi, John Creigh, Henry Samueli, Andrew J. Castellano, David Kruse, Avi Madisetti, Nariman Yousefi, Klaas Bult, Patrick Pai, Myles Wakayama, Mike M. McConnell, Marty Colombatt
1997 J jnl
An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm
IEEE J. Solid State Circuits
Klaas Bult, Aaron Buchwald
1992 J jnl
An inherently linear and compact MOST-only current division technique.
IEEE J. Solid State Circuits
Klaas Bult, Govert J. G. M. Geelen
1990 J jnl
A fast-settling CMOS op amp for SC circuits with 90-dB DC gain.
IEEE J. Solid State Circuits
Klaas Bult, Govert J. G. M. Geelen
1989 J jnl
Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model.
IEEE J. Solid State Circuits
Hans Wallinga, Klaas Bult
1988 J jnl
A CMOS analog continuous-time delay line with adaptive delay-time control.
IEEE J. Solid State Circuits
Klaas Bult, Hans Wallinga