Kjell O. Jeppson

20 papers A* 1A 1C 1Journal 10Unranked 7
YearRankTypeTitle / Venue / Authors
2014 — conf
Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration.
EWME
Per Larsson-Edefors, Kjell O. Jeppson
2013 — conf
A learning tool MOSFET model: A stepping-stone from the square-law model to BSIM4.
PATMOS
Kjell O. Jeppson
2013 — conf
Exploring prefix-tree adders using excel spreadsheets Setting up an explorative learning environment.
MSE
Kjell O. Jeppson, Per Larsson-Edefors
2008 — conf
Noise Interaction Between Power Distribution Grids and Substrate.
ISQED
Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson
2007 — conf
A Student-Oriented Course in Digital VLSI Design.
MSE
Kjell O. Jeppson
2007 — conf
Evaluation of using active circuitry for substrate noise suppression.
ACM Great Lakes Symposium on VLSI
Rashid Farivar, Simon Kristiansson, Fredrik Ingvarson, Kjell O. Jeppson
2006 C conf
Properties and modeling of ground structures for reducing substrate noise coupling in ICs.
ISCAS
Simon Kristiansson, Fredrik Ingvarson, Kjell O. Jeppson
2005 J jnl
A surface potential model for predicting substrate noise coupling in integrated circuits.
IEEE J. Solid State Circuits
Simon Kristiansson, Fredrik Ingvarson, Shiva Prasad Kagganti, Nebojsa Simic, Marinel Zgrda, Kjell O. Jeppson
2004 — conf
A surface potential model for predicting substrate noise coupling in integrated circuits.
CICC
Simon Kristiansson, Fredrik Ingvarson, Shiva Prasad Kagganti, Kjell O. Jeppson
1996 J jnl
Comments on the metastable behavior of mismatched CMOS latches.
IEEE J. Solid State Circuits
Kjell O. Jeppson
1994 J jnl
Comments on the optimum CMOS tapered buffer problem.
IEEE J. Solid State Circuits
Nils Hedenstiema, Kjell O. Jeppson
1994 J jnl
Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay.
IEEE J. Solid State Circuits
Kjell O. Jeppson
1993 J jnl
Comments on 'A module generator for optimized CMOS buffers'.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nils Hedenstierna, Kjell O. Jeppson
1993 J jnl
Formal definitions of edge-based geometric design rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kjell O. Jeppson, Sven Christensson, Nils Hedenstierna
1993 J jnl
The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nils Hedenstierna, Kjell O. Jeppson
1989 A* conf
The Use of Inverse Layout Trees for Hierarchical Design Rule Checking.
DAC
Nils Hedenstierna, Kjell O. Jeppson
1988 J jnl
A corner-based hierarchical circuit extractor.
Integr.
Nils Hedenstierna, Kjell O. Jeppson
1988 A conf
The use of inverse layout trees for hierarchical design verification.
ICCAD
Nils Hedenstierna, Kjell O. Jeppson
1987 J jnl
CMOS Circuit Speed and Buffer Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nils Hedenstierna, Kjell O. Jeppson
1987 J jnl
New algorithms for increased efficiency in hierarchical design rule checking.
Integr.
Nils Hedenstierna, Kjell O. Jeppson